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參數(shù)資料
| 型號： | SN54LV4053A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Quad OR Gate; Package: SOIC 14 LEAD; No of Pins: 14; Container: Rail; Qty per Container: 55 |
| 中文描述： | 三重2通道模擬多路復(fù)用器/解復(fù)用器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 558K |
| 代理商： | SN54LV4053A |
SCLS430K MAY 1999 REVISED APRIL 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
TEST
TA = 25
°
C
TYP
SN54LV4053A
MIN
SN74LV4053A
MIN
UNIT
(OUTPUT)
CONDITIONS
MIN
MAX
MAX
MAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation
delay time
COM or Yn
Yn or COM
CL = 15 pF
(see Figure 4)
1.6
6
10
10
ns
Enable
delay time
INH
COM or Yn
CL = 15 pF
(see Figure 5)
5.3
12
15
15
ns
Disable
delay time
INH
COM or Yn
CL = 15 pF
(see Figure 5)
6.1
12
15
15
ns
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF
(see Figure 4)
2.9
9
12
12
ns
Enable
delay time
INH
COM or Yn
CL = 50 pF
(see Figure 5)
6.1
20
25
25
ns
Disable
delay time
INH
COM or Yn
CL = 50 pF
(see Figure 5)
8.9
20
25
25
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
TEST
TA = 25
°
C
TYP
SN54LV4053A
MIN
SN74LV4053A
MIN
UNIT
(OUTPUT)
CONDITIONS
MIN
MAX
MAX
MAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation
delay time
COM or Yn
Yn or COM
CL = 15 pF
(see Figure 4)
0.9
4
7
7
ns
Enable delay
time
INH
COM or Yn
CL = 15 pF
(see Figure 5)
3.8
8
10
10
ns
Disable
delay time
INH
COM or Yn
CL = 15 pF
(see Figure 5)
4.6
8
10
10
ns
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF
(see Figure 4)
1.8
6
8
8
ns
Enable delay
time
INH
COM or Yn
CL = 50 pF
(see Figure 5)
4.3
14
18
18
ns
Disable
delay time
INH
COM or Yn
CL = 50 pF
(see Figure 5)
6.3
14
18
18
ns
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