參數(shù)資料
型號： SN54LV175AW
廠商： Texas Instruments, Inc.
英文描述： QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
中文描述： 翻兩番D型倒裝，沒有明確的觸發(fā)器
文件頁數(shù)： 1/8頁
文件大?。?/td> 154K
代理商： SN54LV175AW
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400B – APRIL 1998 – REVISED OCTOBER 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Contain Four Flip-Flops With Double-Rail
Outputs
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
The ’LV175A devices are quadruple D-type
flip-flops designed for 2-V to 5.5-V V
CC
operation.
These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
The SN54LV175A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LV175A is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLR
CLK
D
Q
Q
L
X
↑
↑
L
X
L
H
H
H
H
L
H
L
L
H
H
X
Q0
Q0
SN54LV175A . . . J OR W PACKAGE
SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV175A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4Q
4D
NC
3D
3Q
1Q
1D
NC
2D
2Q
1
C
N
C
3
4
2
G
N
V
C
NC – No internal connection
Copyright
1998, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
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