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參數(shù)資料
| 型號： | SN54LV163A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Single 2 Input OR Gate; Package: TSOP-5 / SOT23-5; No of Pins: 5; Container: Tape and Reel; Qty per Container: 3000 |
| 中文描述： | 4位同步二進(jìn)制 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 461K |
| 代理商： | SN54LV163A |
SCLS405E APRIL 1998 REVISED DECEMBER 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing
V
CC
= 2.5 V
±
0.2 V (unless otherwise noted) (see Figure 1)
requirements
over
recommended
operating
free-air
temperature
range,
TA = 25
°
C
MIN
SN54LV163A
MIN
SN74LV163A
MIN
UNIT
MAX
MAX
MAX
tw
Pulse duration, CLK high or low
7
7
7
ns
CLR
6
6
6
tsu
Setup time before CLK
↑
Data (A, B, C, and D)
7.5
8.5
8.5
ns
ENP, ENT
9.5
11
11
LOAD low
10
11.5
11.5
th
Hold time, all synchronous inputs after CLK
↑
1.5
1.5
1.5
ns
timing
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
requirements
over
recommended
operating
free-air
temperature
range,
TA = 25
°
C
MIN
SN54LV163A
MIN
SN74LV163A
MIN
UNIT
MAX
MAX
MAX
tw
Pulse duration, CLK high or low
5
5
5
ns
CLR
4
4
4
tsu
Setup time before CLK
↑
Data (A, B, C, and D)
5.5
6.5
6.5
ns
ENP, ENT
7.5
9
9
LOAD low
8
9.5
9.5
th
Hold time, all synchronous inputs after CLK
↑
1
1
1
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
SN54LV163A
SN74LV163A
UNIT
MAX
MIN
MAX
MIN
MAX
tw
Pulse duration, CLK high or low
5
5
5
ns
CLR
3.5
3.5
3.5
tsu
Setup time before CLK
↑
Data (A, B, C, and D)
4.5
4.5
4.5
ns
ENP, ENT
5
6
6
LOAD low
5
6
6
th
Hold time, all synchronous inputs after CLK
↑
1
1
1
ns
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