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參數(shù)資料
| 型號： | SN54LV126AW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Single Inverter, Schmitt Input; Package: SC-88A, SOT-353, SC-70 5 LEAD; No of Pins: 5; Container: Tape and Reel; Qty per Container: 3000 |
| 中文描述： | 翻兩番總線緩沖器門，三態(tài)輸出 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 127K |
| 代理商： | SN54LV126AW |
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
, T
A
= 25
°
C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
These quadruple bus buffer gates are designed
for 2-V to 5.5-V V
CC
operation.
The ’LV126A devices feature independent line
drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE)
input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
The SN54LV126A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74LV126A is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each buffer)
INPUTS
OE
OUTPUT
Y
A
H
H
H
H
L
L
L
X
Z
Copyright
1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
SN54LV126A . . . J OR W PACKAGE
SN74LV126A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1
1
N
3
3
V
4
2
G
N
SN54LV126A . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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| SN54LV126AFK | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
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