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參數(shù)資料
| 型號： | SN54LV123AW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS |
| 中文描述： | 雙RETRIGGERABLE單穩(wěn)多諧振蕩器與施密特觸發(fā)輸入 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 224K |
| 代理商： | SN54LV123AW |
SN54LV123A, SN74LV123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
SCLS393A – APRIL 1998 – REVISED DECEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Process
Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
The ’LV123A devices are dual retriggerable
monostable multivibrators designed for 2-V to
5.5-V V
CC
operation.
These edge-triggered multivibrators feature
output pulse-duration control by three methods. In
the first method, the A input is low and the B input
goes high. In the second method, the B input is
high and the A input goes low. In the third method,
the A input is low, the B input is high, and the clear
(CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C
ext
and R
ext
/C
ext
(positive) and an external resistor
connected between R
ext
/C
ext
and V
CC
. To obtain variable pulse durations, connect an external variable
resistance between R
ext
/C
ext
and V
CC
. The output pulse duration can also be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Copyright
1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV123A . . . J OR W PACKAGE
SN74LV123A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV123A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1B
1CLR
1Q
2Q
2C
ext
2R
ext
/C
ext
GND
V
CC
1R
ext
/C
ext
1C
ext
1Q
2Q
2CLR
2B
2A
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1C
ext
1Q
NC
2Q
2CLR
1CLR
1Q
NC
2Q
2C
ext
1
1
N
2
2
V
1
2
G
N
C
NC – No internal connection
e
/
e
e
/
e
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
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