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參數(shù)資料
| 型號(hào)： | SN54LS77J |
| 廠商： | MOTOROLA INC |
| 元件分類： | 鎖存器 |
| 英文描述： | LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP14 |
| 封裝： | 632-08 |
| 文件頁(yè)數(shù)： | 4/4頁(yè) |
| 文件大小： | 70K |
| 代理商： | SN54LS77J |
5-4
FAST AND LS TTL DATA
SN54/74LS75
D SN54/74LS77
LOGIC DIAGRAM
DATA
ENABLE
TO OTHER LATCH
Q (SN54/74LS75 ONLY)
Q
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
–55
0
25
125
70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Sb l
P
Limits
Ui
T
C
di i
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Enable Pulse Width High
20
ns
V5 0 V
ts
Setup Time
20
ns
VCC = 5.0 V
th
Hold Time
0
ns
AC WAVEFORMS
D
E
Q
1.3 V
th
ts
tPLH
tPHL
tPLH
tPHL
tPLH
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
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