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參數(shù)資料
| 型號(hào)： | SN54HCT126 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 中文描述： | 翻兩番總線緩沖器門，三態(tài)輸出 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 92K |
| 代理商： | SN54HCT126 |
SN54HCT126, SN74HCT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS070A – NOVEMBER 1988 – REVISED NOVEMBER 1990
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
High-Current 3-State Outputs Drive Bus
Lines or Buffer Memory Address Registers
Inputs Are TTL-Voltage Compatible
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These bus buffers feature independent line
drivers with 3-state outputs. Each output is
disabled when the associated OE is low.
The SN54HCT126 is characterized for operation
over the full military temperature range of –55
°
C
to 125
°
C. The SN74HCT126 is characterized for
operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
OE
OUTPUT
Y
A
H
H
H
H
L
L
L
X
Z
H = high level, L = low level,
X = irrelevant
logic symbol
EN
1
2
1A
1Y
3
4
5
2A
2Y
6
10
9
3A
3Y
8
13
12
4A
4Y
11
1OE
2OE
3OE
4OE
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram, each buffer (positive logic)
OE
A
Y
Copyright
1990, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1
1
N
3
3
V
4
2
G
N
SN54HCT126 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
SN54HCT126 . . . J PACKAGE
SN74HCT126 . . . D OR N PACKAGE
(TOP VIEW)
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