
DEVICE SELECTION GUIDE
HCT
5–93
DEVICE
NO.
PINS
DESCRIPTION
AVAILABILITY
LITERATURE
REFERENCE
DEVICE
NO.
PINS
DESCRIPTION
MIL
PDIP
SOIC
SSOP
TSSOP
TVSOP
LITERATURE
REFERENCE
CD74HCT00
14
Quad 2-Input NAND Gates
SCHS116
SN74HCT00
14
Quad 2-Input NAND Gates
SCLS062
CD74HCT02
14
Quad 2-Input NOR Gates
SCHS125
SN74HCT02
14
Quad 2-Input NOR Gates
SCLS065
CD74HCT03
14
Quad 2-Input NAND Gates with Open-Drain Outputs
SCHS126
CD74HCT04
14
Hex Inverters
SCHS117
SN74HCT04
14
Hex Inverters
SCLS042
CD74HCT08
14
Quad 2-Input AND Gates
SCHS118
SN74HCT08
14
Quad 2-Input AND Gates
SCLS063
CD74HCT10
14
Triple 3-Input NAND Gates
SCHS128
CD74HCT11
14
Triple 3-Input AND Gates
SCHS273
CD74HCT14
14
Hex Schmitt-Trigger Inverters
SCHS129
SN74HCT14
14
Hex Schmitt-Trigger Inverters
SCLS225
CD74HCT20
14
Dual 4-Input NAND Gates
SCHS130
CD74HCT21
14
Dual 4-Input AND Gates
SCHS131
CD74HCT27
14
Triple 3-Input NOR Gates
SCHS132
CD74HCT30
14
8-Input NAND Gates
SCHS121
CD74HCT32
14
Quad 2-Input OR Gates
SCHS274
SN74HCT32
14
Quad 2-Input OR Gates
SCLS064
CD74HCT42
16
4-Line BCD-to-10-Line Decimal Decoders
SCHS133
CD74HCT73
14
Dual J-K Edge-Triggered Flip-Flops with Reset
SCHS134
CD74HCT74
14
Dual D-Type Flip-Flops with Set and Reset
SCHS124
SN74HCT74
14
Dual D-Type Flip-Flops with Set and Reset
SCLS169
SN74HCT74A
14
Dual D-Type Flip-Flops with Set and Reset
Call
CD74HC75
16
Dual 2-Bit Bistable Transparent Latches
SCHS135
CD74HCT85
16
4-Bit Magnitude Comparators
SCHS136
CD74HCT86
14
Quad 2-Input Exclusive-OR Gates
SCHS137
CD74HCT93
14
4-Bit Binary Ripple Counters
SCHS138
CD74HCT107
14
Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
SCHS139
CD74HCT109
16
Dual Positive-Edge-Triggered J-K Flip Flops with Set and Reset
SCHS140
CD74HCT112
16
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
SCHS141
CD74HCT123
16
Dual Retriggerable Monostable Multivibrators with Reset
SCHS142
CD74HCT125
14
Quad Bus Buffers with 3-State Outputs
SCHS143
SN74HCT125
14
Quad Bus Buffers with 3-State Outputs
SCLS069
CD74HCT126
14
Quad Bus Buffers with 3-State Outputs
SCHS144
LFBGA (low-profile fine-pitch ball grid array)
GKE = 96 pins
GKF = 114 pins
TVSOP (thin very small-outline package)
DGV = 14/16/20/24/48/56 pins
DBB = 80 pins
commercial package description and availability
schedule
PDIP (plastic dual-in-line package)
P = 8 pins
N = 14/16/20 pins
NT = 24/28 pins
VFBGA (very-thin-profile fine-pitch ball grid array)
GQL = 56 pins (also includes 48-pin functions)
QFP (quad flatpack)
RC = 52 pins (FB only)
PH = 80 pins (FIFO only)
PQ = 100/132 pins (FIFO only)
TQFP (plastic thin quad flatpack)
PAH
= 52 pins
PAG
= 64 pins (FB only)
PM
= 64 pins
PN
= 80 pins
PCA, PZ = 100 pins (FB only)
PCB
= 120 pins (FIFO only)
SSOP (shrink small-outline package)
DB
= 14/16/20/24/28/30/38 pins
DBQ = 16/20/24
DL
= 28/48/56 pins
SOIC (small-outline integrated circuit)
D
= 8/14/16 pins
DW = 16/20/24/28 pins
= Now
' = Planned
SOT (small-outline transistor)
DBV = 5 pins
DCK = 5 pins
QSOP (quarter-size outline package)
DBQ = 16/20/24 pins
TSSOP (thin shrink small-outline package)
PW = 8/14/16/20/24/28 pins
DGG = 48/56/64 pins
PLCC (plastic leaded chip carrier)
FN = 20/28/44/68/84 pins
See Appendix A for package information on CD54/74HCT devices.