參數(shù)資料
型號： SN54HC174
廠商： Texas Instruments, Inc.
英文描述： Hex Positive-Edge-Triggered D-Type Flip-Flops With Clear(六上升沿D觸發(fā)器(有清除端))
中文描述： 六角上升沿觸發(fā)D型觸發(fā)器與清除正反器（六上升沿?觸發(fā)器（有清除端））
文件頁數(shù)： 5/6頁
文件大?。?/td> 127K
代理商： SN54HC174
SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119A – DECEMBER 1982 – REVISED JANUARY 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
10%
90%
VCC
0 V
tr
tf
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
VCC
0 V
50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
10%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
10%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤ 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
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