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參數(shù)資料
| 型號(hào)： | SN54HC02W |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE 2-INPUT POSITIVE-NOR GATES |
| 中文描述： | 四2輸入陽性或非門 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 76K |
| 代理商： | SN54HC02W |
SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain four independent 2-input
NOR gates. They perform the Boolean function
Y = A + B or Y = A
B in positive logic.
The SN54HC02 is characterized for operation
over the full military temperature range of –55
°
C
to 125
°
C. The SN74HC02 is characterized for
operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
H
X
L
X
H
L
L
L
H
logic symbol
2
1A
3
1B
1Y
1
5
2A
6
2B
2Y
4
8
3A
9
3B
3Y
10
11
4A
12
4B
4Y
13
≥
1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
logic diagram (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
1A
1B
2Y
2A
2B
GND
V
CC
4Y
4B
4A
3Y
3B
3A
SN54HC02 . . . J OR W PACKAGE
SN74HC02 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4B
NC
4A
NC
3Y
1B
NC
2Y
NC
2A
1
1
N
3
3
V
4
2
G
N
SN54HC02 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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