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參數(shù)資料
| 型號： | SN54F21J |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8Kx8 Nonvolatile SRAM, 10% Voltage Tolerance 28-DIP MODULE -40 to 85 |
| 中文描述： | 雙4輸入陽性與門 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 67K |
| 代理商： | SN54F21J |
SN54HC20, SN74HC20
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1A
1B
1C
1D
1Y
2A
2B
2C
2D
2Y
1
2
4
5
9
10
12
13
6
8
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
CC
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
Continuous output current, I
O
(V
O
= 0 to V
CC
)
Continuous current through V
CC
or GND
Package thermal impedance,
θ
JA
(see Note 2): D package
–0.5 V to 7 V
±
20 mA
±
20 mA
±
25 mA
±
50 mA
86
°
C/W
96
°
C/W
80
°
C/W
113
°
C/W
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54HC20
MIN
NOM
SN74HC20
MIN
NOM
UNIT
MAX
MAX
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
1.5
1.5
VIH
High-level input voltage
3.15
3.15
V
4.2
4.2
0
0.5
0
0.5
VIL
Low-level input voltage
0
1.35
0
1.35
V
0
1.8
0
1.8
VI
VO
Input voltage
0
VCC
VCC
1000
0
VCC
VCC
1000
V
Output voltage
0
0
V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
0
0
tt
Input transition (rise and fall) time
0
500
0
500
ns
0
400
0
400
TA
Operating free-air temperature
–55
125
–40
85
°
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs literature number SCBA004.
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