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| 型號： | SN54BCT8373AFK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Programmable Gamma-Voltage Generator and Vcom Calibrator with Integrated Two-Bank Memory 38-HTSSOP |
| 中文描述： | 掃描測試設備與八路D型鎖存器 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 473K |
| 代理商： | SN54BCT8373AFK |
SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F – JUNE 1990 – REVISED JULY 1996
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POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
SCOPE
Family of Testability Products
Octal Test-Integrated Circuits
Functionally Equivalent to ’F373 and
’BCT373 in the Normal-Function Mode
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
Test Operation Synchronous to Test
Access Port (TAP)
Implement Optional Test Reset Signal by
Recognizing a Double-High-Level Voltage
(10 V) on TMS Pin
SCOPE
Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
– Parallel Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
and Ceramic 300-mil DIPs (JT, NT)
description
The ’BCT8373A scan test devices with octal
D-type latches are members of the Texas
Instruments SCOPE
testability integrated-
circuit family. This family of devices supports IEEE
Standard 1149.1-1990 boundary scan to facilitate
testing of complex circuit board assemblies. Scan
access to the test circuitry is accomplished via the
4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the ’F373 and ’BCT373 octal D-type latches.
The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device
terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect
the functional operation of the SCOPE
octal latches.
In the test mode, the normal operation of the SCOPE
octal latches is inhibited and the test circuitry is enabled
to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary
scan test operations, as described in IEEE Standard 1149.1-1990.
Copyright
1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SCOPE is a trademark of Texas Instruments Incorporated.
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LE
1Q
2Q
3Q
4Q
GND
5Q
6Q
7Q
8Q
TDO
TMS
OE
1D
2D
3D
4D
5D
V
CC
6D
7D
8D
TDI
TCK
SN54BCT8373A . . . JT PACKAGE
SN74BCT8373A . . . DW OR NT PACKAGE
(TOP VIEW)
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12 13
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8D
TDI
TCK
NC
TMS
TDO
8Q
2D
1D
OE
NC
LE
1Q
2Q
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14 15 16 1718
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4
G
N
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3
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5
N
V
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SN54BCT8373A . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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