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參數(shù)資料
| 型號： | SN54AS136FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS |
| 中文描述： | 四2輸入異或與開放蓋茨，集電極輸出 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 39K |
| 代理商： | SN54AS136FK |
SN54ALS136, SN54AS136, SN74ALS136, SN74AS136
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
WITH OPEN-COLLECTOR OUTPUTS
SDAS162 – MARCH 1984–REVISED OCTOBER 1988
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1991, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all
parameters.
Package Options include Plastic “Small
Outline” Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Dependable Texas Instruments Quality and
Reliability
description
These
Exclusive-OR gates with open-collector outputs.
They
perform
the
Y = A
⊕
B = AB + AB in positive logic.
devices
contain
four
independent
Boolean
functions
A common application is a true/complement
element. If one of the inputs is low, the other input
will be reproduced in true form at the output. If one
of the inputs is high, the signal on the other input
will be reproduced inverted at the output.
The SN54ALS136 and SN54AS136 are charac-
terized for operation over the full military
temperature range of –55
°
C to 125
°
C. The
SN74ALS136 and SN74AS136 are characterized
for operation from 0
°
C to 70
°
C.
logic symbol
11
= 1
8
6
3
4B
3B
2B
1B
4A
3A
2A
1A
4Y
3Y
2Y
1Y
1
2
4
5
9
10
12
13
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
SN54ALS136, SN54AS136 . . . J PACKAGE
SN74ALS136, SN74AS136 . . . D OR N PACKAGE
(TOP VIEW)
SN54ALS136, SN54AS136 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
FUNCTION TABLE
(each gate)
OUTPUT
Y
L
H
H
INPUTS
A
L
L
H
H
B
L
H
L
L
H
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1
1
N
3
3
4
2
G
N
C
相關PDF資料 |
PDF描述 |
|---|---|
| SN74AS136D | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS |
| SN74AS136N | Quad Bus Buffer, 3 State; Package: SOEIAJ-14; No of Pins: 14; Container: Rail; Qty per Container: 50 |
| SN74ALS136D | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS |
| SN54AS136J | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS |
| SN54ALS136FK | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS |
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