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參數(shù)資料
| 型號： | SN54ALVTH16821 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops(2.5V/3.3V 20位總線接口觸發(fā)器(三態(tài)輸出)) |
| 中文描述： | 2.5-V/3.3-V 20位總線接口正反器（2.5V/3.3V的20位總線接口觸發(fā)器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 222K |
| 代理商： | SN54ALVTH16821 |
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078A – JULY 1996 – REVISED JULY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
High-Impedance State During Power Up
and Power Down
5-V I/O Compatible
High-Drive Capability (–32 mA/64 mA)
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Auto 3-State Eliminates Bus Current
Loading When Voltage at the Output
Exceeds V
CC
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16821 are 20-bit bus-interface
flip-flops with 3-state outputs designed for 2.5-V or
3.3-V V
CC
operation, but with the capability to
provide a TTL interface to a 5-V system
environment.
The ’ALVTH16821 can be used as two 10-bit
flip-flops or one 20-bit flip-flop. The 20 flip-flops
are edge-triggered D-type flip-flops. On the
positive transition of the clock (CLK), the flip-flops
store the logic levels set up at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright
1996, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2D10
2CLK
SN54ALVTH16821 . . . WD PACKAGE
SN74ALVTH16821 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Widebus is a trademark of Texas Instruments Incorporated.
P
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