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參數(shù)資料
| 型號： | SN54ALVTH162827WD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CAPACITOR, ALUMINUM ELECTROLYTIC, CAPACITANCE 10uF, TOLERANCE +/-20%, WVDC 50 VOLTS DC |
| 中文描述： | 2.5-V/3.3-V 20位緩沖器/ 3司機(jī)態(tài)輸出 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 265K |
| 代理商： | SN54ALVTH162827WD |
SN54ALVTH162827, SN74ALVTH162827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES079E – JULY 1996 – REVISED DECEMBER 1998
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer
section, the two output-enable (1OE1 and 1OE2, or 2OE1 and 2OE2) inputs must be low for the corresponding
Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the
high-impedance state.
When V
CC
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
All outputs are designed to sink up to 12 mA, and include equivalent 30-
resistors to reduce overshoot and
undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH162827 is characterized for operation over the full military temperature range of –55
°
C to
125
°
C. The SN74ALVTH162827 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each 10-bit section)
INPUTS
OE2
OUTPUT
Y
OE1
A
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
logic diagram (positive logic)
1Y1
2
1
55
1OE1
1OE2
56
2Y1
15
28
42
29
2OE1
2OE2
To Nine Other Channels
To Nine Other Channels
1A1
2A1
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