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參數(shù)資料
| 型號(hào)： | SN54ALS74AFK |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| 中文描述： | 雙上升沿觸發(fā)的，有清除和預(yù)設(shè)功能的D型觸發(fā)器 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大小： | 114K |
| 代理商： | SN54ALS74AFK |
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
TYPE
TYPICAL MAXIMUM
CLOCK FREQUENCY
(CL = 50 pF)
(MHz)
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
(mW)
′
ALS74A
′
AS74A
50
6
134
26
description
These
positive-edge-triggered D-type flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time of
CLK. Following the hold-time interval, data at the
D input can be changed without affecting the
levels at the outputs.
devices
contain
two
independent
The
characterized for operation over the full military
temperature range of –55
°
C to 125
°
C. The
SN74ALS74A and SN74AS74A are characterized
for operation from 0
°
C to 70
°
C.
SN54ALS74A
and
SN54AS74A
are
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
H
L
L
X
↑
↑
L
X
H
H
H
H
H
L
H
H
L
L
H
H
H
X
Q0
Q0
The output levels in this configuration are not
specified to meet the minimum levels for VOH if the
lows at PRE and CLR are near VIL maximum.
Furthermore, this configuration is nonstable; that
is, it does not persist when PRE or CLR returns to
its inactive (high) level.
SN54ALS74A, SN54AS74A . . . J PACKAGE
SN74ALS74A, SN74AS74A . . . D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54ALS74A, SN54AS74A . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1
1
N
2
2
V
2
1
N
NC – No internal connection
G
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54AS74AFK | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| SN54ALS805AFK | HEX 2-INPUT NOR DRIVERS |
| SN54AS805BJ | HEX 2-INPUT NOR DRIVERS |
| SN74ALS805ADW | HEX 2-INPUT NOR DRIVERS |
| SN74ALS805AN | HEX 2-INPUT NOR DRIVERS |
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