參數(shù)資料
型號: SN54ALS01J
廠商: Texas Instruments, Inc.
英文描述: QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS
中文描述: 四2輸入陽性與開放的NAND蓋茨集電極輸出
文件頁數(shù): 1/3頁
文件大?。?/td> 42K
代理商: SN54ALS01J
SN54ALS01, SN74ALS01
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-COLLECTOR OUTPUTS
SDAS188 – D2661, APRIL 1982 – REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1986, Texas Instruments Incorporated
5BASIC
1
Package Options Include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean functions
Y = A
B or Y = A+B in positive logic. The
open-collector outputs require pullup resistors to
perform correctly. They may be connected to other
open-collector outputs to implement active-low
wired-OR or active-high wired-AND functions.
Open-collector devices are often used to generate
higher V
OH
levels.
The SN54ALS01 is characterized for operation
over the full military temperature range of –55
°
C
to 125
°
C. The SN74ALS01 is characterized for
operation from 0
°
C to 70
°
C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
L
H
H
logic symbol
&
134Y
103Y
42Y
1Y
1
4B
12
4A
11
3B
9
3A
8
2B
6
2A
5
3
1B
1A
2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
4A
4B
4Y
3A
3B
3Y
2A
2B
2Y
1Y
1B
1A
logic diagram (positive logic)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
1A
1B
2Y
2A
2B
GND
V
CC
4Y
4B
4A
3Y
3B
3A
SN54ALS01 . . . J PACKAGE
SN74ALS01 . . . D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4B
NC
4A
NC
3Y
1B
NC
2Y
NC
2A
SN54ALS01 . . . FK PACKAGE
(TOP VIEW)
1
1
N
3
3
4
2
G
N
NC–No internal connection
V
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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