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參數(shù)資料
| 型號： | SN54AHCT126W |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 中文描述： | 翻兩番總線緩沖器門，三態(tài)輸出 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 556K |
| 代理商： | SN54AHCT126W |
SN54AHCT126, SN74AHCT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS265O – DECEMBER 1995 – REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
description/ordering information
The ’AHCT126 devices are quadruple bus buffer
gates featuring independent line drivers with
3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low. When
OE is high, the respective gate passes the data
from the A input to its Y output.
To ensure the high-impedance state during power
up or power down, OE should be tied to GND
through a pulldown resistor; the minimum value of
the resistor is determined by the current-sourcing
capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74AHCT126N
SN74AHCT126N
SOIC – D
Tube
SN74AHCT126D
AHCT126
Tape and reel
SN74AHCT126DR
–40
°
C to 85
°
C
SOP – NS
Tape and reel
SN74AHCT126NSR
AHCT126
SSOP – DB
Tape and reel
SN74AHCT126DBR
HB126
TSSOP – PW
Tube
SN74AHCT126PW
HB126
Tape and reel
SN74AHCT126PWR
TVSOP – DGV
Tape and reel
SN74AHCT126DGVR
HB126
CDIP – J
Tube
SNJ54AHCT126J
SNJ54AHCT126J
–55
°
C to 125
°
C
CFP – W
Tube
SNJ54AHCT126W
SNJ54AHCT126W
LCCC – FK
Tube
SNJ54AHCT126FK
SNJ54AHCT126FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
SN54AHCT126 . . . J OR W PACKAGE
SN74AHCT126 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1
1
N
3
3
V
4
2
G
N
SN54AHCT126 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54AHCT132 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS |
| SN54AHCT132_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS |
| SN54AHCT132FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS |
| SN54AHCT132J | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS |
| SN54AHCT132W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS |
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