參數(shù)資料
型號(hào)： SN54AHCT123AW
廠商： Texas Instruments, Inc.
英文描述： DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
中文描述： 雙RETRIGGERABLE單穩(wěn)態(tài)多頻振蕩器
文件頁(yè)數(shù)： 2/21頁(yè)
文件大?。?/td> 570K
代理商： SN54AHCT123AW
SN54AHCT123A, SN74AHCT123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS420G
–
JUNE 1998
–
REVISED APRIL 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information(continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR input can be used to override
A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early
clearing.
The variance in output pulse duration from device to device typically is less than
±
0.5% for given external timing
components. An example of this distribution for the
’
AHCT123A is shown in Figure 10. Variations in output pulse
duration versus supply voltage and temperature are shown in Figure 6.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
For additional application information on multivibrators, see the application report,
Designing With the
SN74AHC123A and SN74AHCT123A
, literature number SCLA014.
FUNCTION TABLE
(each multivibrator)
INPUTS
OUTPUTS
CLR
A
B
Q
Q
L
X
X
L
L
L
H
H
H
X
H
X
X
X
L
↑
H
H
L
H
↑
L
H
These outputs are based on the
assumption
that
steady-state conditions at the A and
B inputs have been set up long enough to
complete any pulse started before the
setup.
the
indicated
logic diagram, each multivibrator (positive logic)
CLR
Cext
Rext/Cext
R
B
A
Q
Q
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