參數(shù)資料
型號(hào)： SN54AHCT02FK
廠商： Texas Instruments, Inc.
英文描述： QUADRUPLE 2-INPUT POSITIVE-NOR GATES
中文描述： 四2輸入陽(yáng)性或非門(mén)
文件頁(yè)數(shù)： 2/6頁(yè)
文件大?。?/td> 83K
代理商： SN54AHCT02FK
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
2
1A
3
1B
1Y
1
5
2A
6
2B
2Y
4
8
3A
9
3B
3Y
10
11
4A
12
4B
4Y
13
≥
1
logic diagram (positive logic)
2
1A
3
1B
1Y
1
8
3A
9
3B
3Y
10
5
2A
6
2B
2Y
4
11
4A
12
4B
4Y
13
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, V
I
(see Note 1)
Output voltage range, V
O
(see Note 1)
Input clamp current, I
IK
(V
I
< 0)
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
Continuous output current, I
O
(V
O
= 0 to V
CC
)
Continuous current through V
CC
or GND
Package thermal impedance,
θ
JA
(see Note 2): D package
–0.5 V to 7 V
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to V
CC
+ 0.5 V
–
20 mA
±
20 mA
±
25 mA
±
50 mA
86
°
C/W
96
°
C/W
127
°
C/W
80
°
C/W
113
°
C/W
–65
°
C to 150
°
C
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