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參數(shù)資料
| 型號： | SN54AHC163 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Synchronous Binary Counters(4位二進制同步計數(shù)器) |
| 中文描述： | 4位同步二進制計數(shù)器（4位二進制同步計數(shù)器） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 291K |
| 代理商： | SN54AHC163 |
SN54AHC163, SN74AHC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS369A – MAY 1997 – REVISED JUNE 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Operating Range 2-V to 5.5-V V
CC
EPIC
(Enhanced-Performance Implanted
CMOS) Process
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The ’AHC163 are
4-bit binary counters. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change
coincident with each other when instructed by the
count-enable (ENP, ENT) inputs and internal
gating. This mode of operation eliminates the
output counting spikes normally associated with
synchronous (ripple-clock) counters. A buffered
clock (CLK) input triggers the four flip-flops on the
rising (positive-going) edge of the clock
waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’AHC163 is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop
outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q
A
high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
P
Copyright
1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
SN54AHC163 . . . J OR W PACKAGE
SN74AHC163 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
SN54AHC163 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Q
A
Q
B
NC
Q
C
Q
D
A
B
NC
C
D
C
C
N
L
E
R
E
G
N
V
C
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PDF描述 |
|---|---|
| SN74AHC163 | 4-Bit Synchronous Binary Counters(4位二進制同步計數(shù)器) |
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| SN54AHC257J | QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS |
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