
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556A – NOVEMBER 1995 – REVISED MAY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
3-State Inverting Outputs Drive Bus Lines
Directly
Full Parallel Access for Loading
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively low-imped-
ance loads. The devices are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the complements of the
logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-
impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup
components.
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ACT534 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74ACT534 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK
↑
↑
H or L
OUTPUT
Q
OE
D
L
H
L
L
L
H
L
X
Q0
Z
H
X
X
Copyright
1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ACT534 . . . J OR W PACKAGE
SN74ACT534 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
SN54ACT534 . . . FK PACKAGE
(TOP VIEW)
1
1
O
5
5
8
4
G
C
V
C