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參數(shù)資料
| 型號： | SN54ACT1284 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 7-Bit Bus Interfaces With 3-State Outputs(7位總線接口(三態(tài)輸出)) |
| 中文描述： | 7與3位總線接口態(tài)輸出（7位總線接口（三態(tài)輸出）） |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 121K |
| 代理商： | SN54ACT1284 |
SN54ACT1284, SN74ACT1284
7-BIT BUS INTERFACES
WITH 3-STATE OUTPUTS
SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
tPHL
tPLH
From B Output
Under Test
A-TO-B LOAD (totem pole)
1.5 V
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
3 V
VOH
VOL
0 V
62
CL = 50 pF
(see Note A)
33
TP1
VCC
CL = 50 pF
(see Note A)
Sink Load
Source Load
1.5 V
VOH
VOL
VOH – 1.4 V
VOL + 1.4 V
62
tPHL
tPLH
tf
A-TO-B LOAD (open drain)
1.5 V
VOLTAGE WAVEFORMS MEASURED AT TP1 (B SIDE)
3 V
VOH
VOL
0 V
TP1
VCC
CL = 50 pF
(see Note A)
1.5 V
VOL
(see Note E)
0.8 V
500
From B Output
tr
2 V
2 V
0.8 V
tPHL
tPLH
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
3 V
VOH
VOL
0 V
1.5 V
Output
50% VCC
B-TO-A LOAD (totem pole)
CL = 50 pF
(see Note A)
500
From A Output
Under Test
Input
(see Note C)
Output
(see Note D)
Input
(see Note F)
Input
(see Note F)
NOTES: A. CL includes probe and jig capacitance.
B. The outputs are measured one at a time with one transition per measurement.
C. Input rise and fall times are 3 ns, 150 ns < pulsewidth <10
μ
s for both low-to-high and high-to-low transitions.
D. Slew rate is defined as 10% and 90% of the transition times.
E. Rise and fall times, open drain, are <120 ns.
F. Input rise and fall times are 3 ns.
Figure 1. Load Circuits and Voltage Waveforms
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