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參數(shù)資料
| 型號(hào)： | SN54ABT854 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit To 9-Bit Parity Bus Transceivers(8-9奇偶總線收發(fā)器) |
| 中文描述： | 8位到第9位奇偶總線收發(fā)器（8-9奇偶總線收發(fā)器） |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 142K |
| 代理商： | SN54ABT854 |
SN54ABT854, SN74ABT854
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS170 – FEBRUARY 1991–REVISED OCTOBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1992, Texas Instruments Incorporated
1
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 1 V at V
CC
= 5 V, T
A
= 25
°
C
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
Parity Error Flag With Parity
Generator/Checker
Latch for Storage of the Parity Error Flag
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
The ’ABT854 8-bit to 9-bit parity transceiver is
designed for communication between data buses.
When data is transmitted from the A bus to the B
bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR) output indicates whether or not
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT854 provides
inverted data at its outputs.
A 9-bit parity generator/checker generates a
parity-odd (PARITY) output and monitors the
parity of the I/O ports with the ERR flag. The
parity-error output can be passed, sampled,
stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs.
When both OEA and OEB are low, data is
transferred from the A bus to the B bus and
inverted parity is generated. Inverted parity is a
forced error condition that gives the designer more
system diagnostic capability.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT854 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74ABT854 is characterized for operation from –40
°
C to 85
°
C.
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9
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24
23
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13
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE
SN54ABT854 . . . JT PACKAGE
SN74ABT854 . . . DW OR NT PACKAGE
(TOP VIEW)
NC – No internal connection
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
B3
B4
B5
NC
B6
B7
B8
A3
A4
A5
NC
A6
A7
A8
4
26
14 15 16 1718
E
C
G
N
L
O
P
A
A
O
N
B
B
SN54ABT854 . . . FK PACKAGE
(TOP VIEW)
V
C
EPIC-
ΙΙ
B is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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|---|---|
| SN74ABT854 | 8-Bit To 9-Bit Parity Bus Transceivers(8-9奇偶總線收發(fā)器) |
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| SN74ABT862 | 10-Bit Bus Transceivers With 3-State Outputs(10位總線收發(fā)器(三態(tài)輸出)) |
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| SN54ABT8996JT | 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS |
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| SN54ABT8543 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
| SN54ABT8543FK | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
| SN54ABT8543JT | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
| SN54ABT861 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:10-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN54ABT861FK | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:10-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS |
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