參數(shù)資料
型號(hào): SN54ABT16651
廠(chǎng)商: Texas Instruments, Inc.
英文描述: 16-Bit Bus Transceivers and Registers With 3-State Outputs(16位總線(xiàn)收發(fā)器和寄存器(三態(tài)輸出))
中文描述: 16位總線(xiàn)收發(fā)器和寄存器具有三態(tài)輸出(16位總線(xiàn)收發(fā)器和寄存器(三態(tài)輸出))
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 183K
代理商: SN54ABT16651
SN54ABT16651, SN74ABT16651
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS214 – OCTOBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3–2
description (continued)
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The SN74ABT16651 is available in TI’s shrink small-outline package (DL), which provides twice the I/O pin
count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT16651 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74ABT16651 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
H
CLKAB
CLKBA
SAB
SBA
A1 THRU A8
B1 THRU B8
L
H or L
H or L
X
H or L
H or L
X
X
X
Input
Input
Isolation
L
H
X
X
Input
Input
Store A and B data
X
H
X
X
X
Input
Unspecified
Store A, hold B
H
H
X
Input
Output
Store A in both registers
L
X
X
X
X
Unspecified
Input
Hold A, store B
L
L
X
Output
input
Store B in both registers
L
L
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Output
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
When select control is low, clocks can occur simultaneously so long as allowances are made for propagation delays from A to B (B to A) plus
setup and hold times. When select control is high, clocks must be staggered in order to load both registers.
P
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參數(shù)描述
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