參數(shù)資料
型號: SN54ABT125J
廠商: Texas Instruments, Inc.
英文描述: High Speed, Closed Loop Buffer 8-SOIC -45 to 85
中文描述: 翻兩番總線緩沖器門,三態(tài)輸出
文件頁數(shù): 1/18頁
文件大?。?/td> 642K
代理商: SN54ABT125J
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Typical V
OLP
(Output Ground Bounce)
<1 V at V
CC
= 5 V, T
A
= 25
°
C
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
I
off
and Power-Up 3-State Support Hot
Insertion
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SN54ABT125 . . . J OR W PACKAGE
SN74ABT125 . . . D, DB, N, NS,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1
1
N
3
3
V
4
2
G
N
SN54ABT125 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
SN74ABT125 . . . RGY PACKAGE
(TOP VIEW)
1
14
7
8
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1
3
V
G
description/ordering information
The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE) input is high.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74ABT125N
SN74ABT125N
QFN – RGY
Tape and reel
SN74ABT125RGYR
AB125
SOIC – D
Tube
SN74ABT125D
ABT125
–40
°
C to 85
°
C
Tape and reel
SN74ABT125DR
SOP – NS
Tape and reel
SN74ABT125NSR
ABT125
SSOP – DB
Tape and reel
SN74ABT125DBR
AB125
TSSOP – PW
Tape and reel
SN74ABT125PWR
AB125
CDIP – J
Tube
SNJ54ABT125J
SNJ54ABT125J
–55
°
C to 125
°
C
CFP – W
LCCC – FK
Tube
Tube
SNJ54ABT125W
SNJ54ABT125FK
SNJ54ABT125W
SNJ54ABT125FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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