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參數(shù)資料
| 型號： | SN100KT5573 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal ECL-to-TTL Translator With D-Type Transparent Latches and 3-State Outputs(八ECL-TTL轉換器(D觸發(fā)器,三態(tài)輸出)) |
| 中文描述： | 八路ECL至TTL電翻譯與D類透明鎖存器和三態(tài)輸出（八電化學發(fā)光的TTL轉換器（深觸發(fā)器，三態(tài)輸出）） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 124K |
| 代理商： | SN100KT5573 |
SN100KT5573
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
TRANSPARENT LATCHES AND 3-STATE OUTPUTS
SDZS016 – MAY 1990 – REVISED OCTOBER 1990
Copyright
1990, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
100K Compatible
ECL and TTL Control Inputs
Noninverting Outputs
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin V
CC
, V
EE
, and GND
Configurations Minimize High-Speed
Switching Noise
Package Options Include “Small Outline”
Packages and Standard Plastic 300-mil
DIPs
description
This octal ECL-to-TTL translator is designed to provide efficient translation between a 100K ECL signal
environment and a TTL signal environment. This device is designed specifically to improve the performance
and density of ECL-to-TTL CPU/bus-oriented functions such as memory address drivers, clock drivers, and bus
oriented receivers and transmitters.
The eight latches of the SN100KT5573 are transparent D-type latches. While latch enable (LE) is low, the Q
outputs follow the data (D) inputs. When LE is high, the Q outputs are latched at the levels that were set up at
the D inputs.
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components. Output-enable OE does not affect the internal operations of
the latches. Old data can be retained or new data can be entered while the outputs are off.
The SN100KT5573 is characterized for operation from 0
°
to 85
°
C.
FUNCTION TABLE
OE
L
L
LE
L
L
OUTPUT
ENABLE
D
L
H
DATA
INPUT
Q
L
H
OUTPUT
(TTL)
L
H
X
QO
Z
H
X
X
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
20
17
24
23
22
21
16
15
14
13
12
11
10
9
4
3
2
1
1D
EN
C1
ECL/TTL
ECL/TTL
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
V
CC
GND
GND
GND
5Q
6Q
7Q
8Q
1D
2D
3D
4D
OE (TTL)
V
EE
GND
LE (ECL)
5D
6D
7D
8D
OR NT PACKAGE
(T0P VIEW)
P
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN100KT5574 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS |
| SN100KT5574DW | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN100KT5578 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE |
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