參數(shù)資料
型號(hào)： SN0305042RTHR
廠商： TEXAS INSTRUMENTS INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 1803 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC24
封裝： GREEN, PLASTIC, VQFN-24
文件頁(yè)數(shù)： 21/26頁(yè)
文件大小： 606K
代理商： SN0305042RTHR
www.ti.com
RS0 = 0
EN
CDCM1804
S1
S0
RS1 = 60 k
REN = Open
Setting for Mode 13:
EN = 1
S2 = VDD/2
S1 = VDD/2
S0 = 0
RS2 = 60 k
S2
S0084-01
CDCM1804
SCAS697E – JULY 2003 – REVISED MAY 2005
Figure 1. Control Terminal Setting for Example
Table 1. Selection Mode Table
LVPECL(1)
LVCMOS
MODE
EN
S2
S1
S0
Y0
Y1
Y2
Y3
0
x
Off (high-z)
1
0
÷ 1
Off (high-z)
2
1
0
VDD/2
÷ 1
Off (high-z)
÷ 4
3
1
0
1
÷ 1
Off (high-z)
÷ 4
4
1
0
VDD/2
0
÷ 1
÷ 2
Off (high-z)
÷ 4
5
1
0
VDD/2
÷ 1
÷ 4
Off (high-z)
÷ 4
6
1
0
VDD/2
1
÷ 1
÷ 8
Off (high-z)
÷ 4
7
1
0
1
0
÷ 1
Off (high-z)
÷ 1
÷ 4
8
1
0
1
VDD/2
÷ 1
÷ 4
9
1
0
1
÷ 1
÷ 2
÷ 1
÷ 4
10
1
VDD/2
0
÷ 1
÷ 4
÷ 1
÷ 4
11
1
VDD/2
0
VDD/2
÷ 1
÷ 8
÷ 1
÷ 4
12
1
VDD/2
0
1
÷ 1
Off (high-z)
÷ 2
÷ 4
13
1
VDD/2
0
÷ 1
÷ 2
÷ 4
14
1
VDD/2
÷ 1
÷ 2
÷ 4
15
1
VDD/2
1
÷ 1
÷ 4
÷ 2
÷ 4
16
1
VDD/2
1
0
÷ 1
÷ 8
÷ 2
÷ 4
17
1
VDD/2
1
VDD/2
÷ 1
Off (high-z)
÷ 4
18
1
VDD/2
1
÷ 1
÷ 4
19
1
0
÷ 1
÷ 2
÷ 4
20
1
0
VDD/2
÷ 1
÷ 4
21
1
0
1
÷ 1
÷ 8
÷ 4
22
1
VDD/2
0
÷ 1
Off (high-z)
÷ 8
÷ 4
23
1
VDD/2
÷ 1
÷ 8
÷ 4
24
1
VDD/2
1
÷ 1
÷ 2
÷ 8
÷ 4
25
1
0
÷ 1
÷ 4
÷ 8
÷ 4
(1)
The LVPECL outputs are open-emitter stages. Thus, if you leave the unused LVPECL outputs Y0, Y1, or Y2 unconnected, then the
current consumption is minimized and noise impact to remaining outputs is neglectable. Also, each output can be individually disabled
by connecting the corresponding VDD input to GND.
4
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