參數(shù)資料
型號(hào)： SMX320C6201BW16
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 浮點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 31/64頁
文件大?。?/td> 939K
代理商： SMX320C6201BW16
SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for CLKOUT2
(see Figure 10)
NO.
PARAMETER
’
C6701-14
’
C6701-16
UNIT
MIN
MAX
1
tc(CKO2)
tw(CKO2H)
tw(CKO2L)
tt(CKO2)
Cycle time, CLKOUT2
*2P
–
0.7
*2P + 0.7
ns
2
Pulse duration, CLKOUT2 high
*P
–
0.7
*P + 0.7
ns
3
Pulse duration, CLKOUT2 low
*P
–
0.7
*P + 0.7
ns
4
Transition time, CLKOUT2
*0.6
ns
P = 1/CPU clock frequency in ns.
*This parameter is not tested.
CLKOUT2
1
2
3
4
4
Figure 10. CLKOUT2 Timings
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 11)
NO.
PARAMETER
’
C6701-14
’
C6701-16
UNIT
MIN
MAX
1
td(CKO1-SSCLK)
td(CKO1-SSCLK1/2)
td(CKO1-CKO2)
td(CKO1-SDCLK)
Delay time, CLKOUT1 edge to SSCLK edge
–
0.8
3.4
ns
2
Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
–
1.0
3.0
ns
3
Delay time, CLKOUT1 edge to CLKOUT2 edge
–
1.5
2.5
ns
4
Delay time, CLKOUT1 edge to SDCLK edge
–
1.5
1.9
ns
4
3
2
1
CLKOUT1
SSCLK
SSCLK (1/2rate)
CLKOUT2
SDCLK
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
相關(guān)PDF資料
PDF描述
SMX320C6203S14 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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相關(guān)代理商/技術(shù)參數(shù)
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