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參數(shù)資料
| 型號(hào)： | SMJL-29C80FHXXX |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQFP44 |
| 封裝： | MQFP-44 |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 287K |
| 代理商： | SMJL-29C80FHXXX |
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29C80F
Rev. D (25 Mar.97)
67
MATRA MHS
Pin Description
Power
VCCA
: Array Positive Supply
pin 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCCB
: Input/Output Buffers Positive Supply
pin 12 & 34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSSA
: Array Negative Supply (0 Volt)
pin 23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSSB
: Input/Output Buffers Negative Supply (0 Volt)
pin 13 & 33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Several power supply pins are provided to minimise
inductance within package. All supplies must be
connected. The supply must be decoupled close to the
chip by at least one 100 nF ceramic capacitor between
each couple VCC/VSS (pin 1 & 23, pin 12 & 13, pin 34
& 33). Four layer boards are recommended (cf figure 13).
If two layer boards are used, a special care should be taken
in decoupling.
System Services
CLK
: Input Clock
pin 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
/CLKEN
: Clock Enable (active low)
pin 4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
/OEN
: Output Enable (active low)
pin 39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK :
The input clock controls the 29C80F
timing. The falling edge of CLK samples
the input data (DI[..]) and the input
commands (BLKIN, F/I, PIX, ZZ &
/CLKEN). The rising edge of CLK drives
the output latches which provide computed
data
(DO[..])
and
output
control
(BLKOUT).
/CLKEN :
The
clock
enable
allows
to
stop
(/CLKEN = VIH) the internal clock.
Sampled on the falling edge of CLK, this
command is taken into account in the next
cycle, this means from the next rising edge.
Then, the internal clocks are stoped and the
output data (DI[..]) and the output control
(BLKIN) are in high impedance regardless
output enable command (/OEN). So,
/CLKEN can be used to reduce the power
consumption.
/OEN :
When output enable in high, all the outputs
(/BLKOUT and DO [..]) are forced in the
high impedance state.
Synchronous Controls
BLKIN
: Block Input Synchronization
pin 43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLKOUT
: Block Output Synchronization
pin 42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F/I
: FDCT/IDCT Selection
pin 3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZZ
: Coefficient Scanning Selection
pin 5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIX
: 8 or 9 Pixel Data Selection
pin 6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLKIN :
BLKIN defines the beginning of a new
input block. It is sampled on the falling
edge of CLK. When BLKIN has been
sampled
high,
the
next
CLK
cycle
corresponds to the first data of the new
input block (if the blocks to be computed
are contiguous, the BLKIN signal must be
generated during the 64th input data of the
previous block).
BLKOUT :
BLKOUT defines the beginning of a new
output block. It is the pipelined BLKIN
signal (1 latent period) provided by the
output latch driven by the rising edge of
CLK. It is active (high level) one CLK
cycle in advance compared to the first data
of corresponding output block (if the
blocks computed were contiguous, the
BLKOUT signal is provided during the
64th output data of the previous block).
F/I :
F/I input defines the type of transform for
the entire block, F/I = VIH for FCDT and
F/I = VIL for IDCT. This selection is
sampled on the falling edge of CLK during
the BKLIN period (cf BLKIN definition).
In order to mixt FDCT and IDCT together,
a minimum gap of 128 CLK periods is
needed between blocks. This means, if a
BKLIN is placed in cycle “-1” for one type
of block (cf figure 10), the BLKIN for the
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