參數(shù)資料
型號(hào)： SMJ626162
廠商： Texas Instruments, Inc.
英文描述： 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
中文描述： 524288由16位2，銀行同步動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器
文件頁(yè)數(shù)： 1/42頁(yè)
文件大?。?/td> 647K
代理商： SMJ626162
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Organization
512K
×
16 Bits
×
2 Banks
3.3-V Power Supply (
±
5% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
High Bandwidth – Up to 83-MHz Data Rates
Read Latency Programmable to
2 or 3 Cycles From Column-Address Entry
Burst Sequence Programmable to Serial or
Interleave
Burst Length Programmable to 1, 2, 4, 8, or
256 (Full Page)
Chip Select and Clock Enable for Enhanced
System Interfacing
Cycle-by-Cycle DQ-Bus Mask Capability
With Upper- and Lower-Byte Control
Autorefresh Capability
4K Refresh (Total for Both Banks)
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
Pipeline Architecture
Temperature Ranges:
Operating, – 55
°
C to 125
°
C
Storage, – 65
°
C to 150
°
C
Performance Ranges:
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK
(MIN)
’626162-12
12 ns
’626162-15
15 ns
’626162-20
20 ns
Read latency = 3
description
ACCESS TIME
CLOCK TO
OUTPUT
tAC
(MIN)
8ns
9ns
10ns
REFRESH
TIME
INTERVAL
tREF
(MAX)
32ms
32ms
32ms
The
16777216-bit synchronous dynamic random-
access memory (SDRAM) devices organized as
two banks of 524288 words with 16 bits per word.
SMJ626162
series
of
devices
are
All inputs and outputs of the SMJ626162 series
are compatible with the LVTTL interface.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PIN NOMENCLATURE
A[0:10]
Address Inputs
A0–A10 Row Addresses
A0–A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
System Clock
Chip Select
SDRAM Data Input/Data Output
Data-Input/Data-Output Mask Enable
No Connect
Row-Address Strobe
Power Supply (3.3-V Typical)
Power Supply for Output Drivers
(3.3-V Typical)
Ground
Ground for Output Drivers
Write Enable
A11
CAS
CKE
CLK
CS
DQ[0:15]
DQML, DQMU
NC
RAS
VCC
VCCQ
VSS
VSSQ
W
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
CCQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
CCQ
NC
DQMU
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
CC
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
CCQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
CCQ
DQML
W
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
HKD PACKAGE
(TOP VIEW)
Copyright
1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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