參數(shù)資料
型號(hào): SMJ4C1024-80SV
廠商: Texas Instruments, Inc.
英文描述: 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
中文描述: 1048576 1位動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器
文件頁(yè)數(shù): 17/27頁(yè)
文件大小: 403K
代理商: SMJ4C1024-80SV
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A9
W
D
Q
tw(RL)P
tw(RH)
tc(PM)
td(RLCH)
td(RLCL)
tw(CH)
tw(CL)
td(CLRH)
td(CHRL)
tsu(CA)
th(RLCA)
td(RLCA)
th(CA)
tsu(RA)
th(RA)
Row
Column
Column
Don’t Care
tsu(rd)
td(CLWL)
td(CAWL)
td(RLWL)
tw(WL)
tsu(WCH)
tsu(WRH)
Don’t Care
th(D)
tsu(D)
Don’t Care
Don’t Care
Valid
Valid
Valid
Out
Valid
Out
ta(C)
ta(CA)
ta(R)
ta(CP)
tdis(CH)
See Note A
See Note A
NOTES: A. Output can go from high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
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