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參數(shù)資料
| 型號： | SMJ44400JD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 100萬× 4的DRAM動態(tài)隨機(jī)存取存儲器 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 351K |
| 代理商： | SMJ44400JD |
DRAM
SMJ44400
Austin Semiconductor, Inc.
SMJ44400
Rev. 2.0 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
(continued)
Power Up (continued)
required after full Vcc level is achieved. These eight initial-
ization cycles need to include at least one refresh (RAS\-only
or CBR) cycle.
Test Mode
An industry standard Design For Test (DFT) mode is
incorporated in the SMJ44400. A CBR with W\ low (WCBR)
cycle is used to enter test mode. In the test mode, data is
written into and read from eight sections of the array in
parallel. All data is written into the array through DQ1. Data
is comparted upon reading and if all bits are equal, all DQ pins
go high. If any one bit is different, all the DQ pins go low.
Any combination read, write, read-write, or page-mode can
be used in the test mode. The test mode function reduces test
times by enabling the 1M x 4-bit DRAM to be tested as if it
were a 512K DRAM where column address 0 is not used. A
RAS\-only or CBR refresh cycle is used to exit the DFT mode.
LOGIC SYMBOL
1
6
7
8
9
11
12
13
14
15
5
4
17
3
16
1
2
18
19
RAM 1024K x 4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS\
CAS\
W\
OE\
DQ1
DQ2
DQ3
DQ4
&
23,21D
G25
20D10/21D0
20D19/21D9
C20[Row]
G23/[Refresh Row]
24[Power Down]
C21[Column]
G24
23C22
24,25EN
A
0
1 048 575
A, 22D
26
A, Z26
1. This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. The pinouts illustrated are for the JD package.
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| SMJ4C1024-10JD | 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY |
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