
SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Organization . . . 4194304
×
4
Single 5-V Power Supply (10% Tolerance)
Performance Ranges:
ACCESS ACCESS ACCESS
TIME
tRAC
(MAX)
’416400-70
70 ns
’416400-80
80 ns
’416400-10
100 ns
Enhanced Page-Mode Operation for Faster
Memory Access
CAS-Before-RAS (CBR) Refresh
Long Refresh Period
4096 Cycles Refresh in 32 ms
3-State Unlatched Output
Low Power Dissipation
All Inputs, Outputs, and Clocks are
TTL-Compatible
Operating Free-Air Temperature Range
– 55
°
C to 125
°
C
READ
OR WRITE
CYCLE
(MIN)
130 ns
150 ns
180 ns
TIME
tCAC
(MAX)
18 ns
20 ns
25 ns
TIME
tAA
(MAX)
35 ns
40 ns
45 ns
description
The SMJ416400 series is a set of high-speed
16777216-bit
dynamic
memories (DRAMs), organized as 4194304
words of four bits each. The series employs
technology for high performance, reliability, and
low power.
random-access
These devices feature maximum RAS access
times of 70 ns, 80 ns, and 100 ns. All inputs,
outputs, and clocks are compatible with series 54
TTL. All addresses and data-in lines are latched
on-chip to simplify system design. Data out is
unlatched to allow greater system flexibility.
The SMJ416400 is offered in 450-mil 24/28-pin
surface-mount small-outline leadless chip carrier
(FNC suffix), 28-lead flatpack (HKB suffix), and
24-lead ZIP (SV suffix) packages. The packages
are characterized for operation from –55
°
C to
125
°
C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
PIN NOMENCLATURE
A0–A11
Address Inputs
CAS
Column-Address Strobe
DQ1–DQ4
Data In/Data Out
NC
No Internal Connection
OE
Output Enable
RAS
Row-Address Strobe
W
Write Enable
VCC
5-V Supply
VSS
Ground
HKB PACKAGE
(TOP VIEW)
V
CC
DQ1
DQ2
W
RAS
A11
NC
NC
A10
A0
A1
A2
A3
V
CC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
SS
DQ4
DQ3
CAS
OE
A9
NC
NC
A8
A7
A6
A5
A4
V
SS
V
CC
DQ1
DQ2
W
RAS
A11
28
27
26
25
24
23
20
19
18
17
16
15
1
2
3
4
5
6
V
SS
DQ4
DQ3
CAS
OE
A9
9
10
11
12
13
14
A10
A0
A1
A2
A3
V
CC
A8
A7
A6
A5
A4
V
SS
FNC PACKAGE
(TOP VIEW)
A9
CAS
DQ3
V
CC
DQ1
RAS
A10
A1
A3
V
SS
A5
A7
2
4
6
8
10
12
14
16
18
20
22
24
1
3
5
7
9
11
13
15
17
19
21
23
OE
DQ2
V
SS
DQ4
W
A11
A0
A2
V
CC
A4
A6
A8
SV PACKAGE
(TOP VIEW)
Copyright
1996, Texas Instruments Incorporated