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參數(shù)資料
| 型號： | SMJ4164-20JDL |
| 英文描述： | x1 Page Mode DRAM |
| 中文描述： | x1頁面模式的DRAM |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 437K |
| 代理商： | SMJ4164-20JDL |
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
self refresh (TMS416100P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100
μ
s. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy t
CHS
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input low
(WCBR). The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel
read or write on subsequent cycles. While in the test mode, any data sequence can be performed. The device
exits the test mode if a CAS-before-RAS (CBR) refresh cycle with W held high or a RAS-only refresh (ROR) cycle
is performed.
The device is configured as 1024K
×
16 bits with a 16-bit parallel read-and-write data path in the test mode.
Column addresses A0, A1, A10, and A11 are not used. During a read cycle, all 16 bits of the internal data bus
are compared. If all bits are in the same data state, the output pin goes high. If one or more bits disagree, the
output pin goes low. Test time is reduced by a factor of 16, compared to normal memory mode.
RAS
CAS
W
Test-Mode Cycle
Entry
Cycle
Exit
Cycle
Normal
Mode
NOTE: The states of W, data input, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
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