參數(shù)資料
型號： SMJ320VC33GNMM150
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 7/54頁
文件大?。?/td> 614K
代理商： SMJ320VC33GNMM150
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
Terminal Functions (Continued)
TERMINAL
TYPE
DESCRIPTION
CONDITIONS
WHEN
SIGNAL IS Z TYPE
NAME
QTY
TIMER SIGNALS
TCLK0
1
I/O/Z
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As
an output, TCLK0 outputs pulses generated by timer 0.
S
R
TCLK1
1
I/O/Z
Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As
an output, TCLK1 outputs pulses generated by timer 1.
S
R
SUPPLY AND OSCILLATOR SIGNALS
H1
1
O/Z
External H1 clock
S
H3
1
O/Z
External H3 clock
S
CV
DD
8
I
+V
DD
. Dedicated 1.8-V power supply for the core CPU. All must be connected to
a common supply plane.
§
DV
DD
16
I
+V
DD
. Dedicated 3.3-V power supply for the I/O pins. All must be connected to a
common supply plane.
§
V
SS
PLLV
DD
PLLV
SS
18
I
Ground. All grounds must be connected to a common ground plane.
1
I
Internally isolated PLL supply. Connect to CV
DD
(1.8 V)
Internally isolated PLL ground. Connect to V
SS
External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is
used, tie this pin to ground.
1
I
EXTCLK
1
I
XOUT
1
O
Clock out. Output from the internal-crystal oscillator. If a crystal is not used, XOUT
should be left unconnected.
XIN
1
I
Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to
ground.
CLKMD0,
CLKMD1
2
I
Clock mode select pins
RSV0 - RSV1
2
I
Reserved. Use individual pullups to DV
DD
.
JTAG EMULATION
EMU1- EMU0
2
I/O
Emulation pins 0 and 1, use individual pullups to DV
DD
Test data input
TDI
1
I
TDO
1
O
Test data output
TCK
1
I
Test clock
TMS
1
I
Test mode select
TRST
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
§
Recommended decoupling. Four 0.1
μ
F for CV
DD
and eight 0.1
μ
F for DV
DD
.
1
I
Test reset
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