
SMJ320C50KGD
DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIE
SGZS007A – JUNE 1996 – REVISED JUNE 1997
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Processed to MIL-PRF-38535
Fast Instruction Cycle Time of 30 ns, 40 ns,
and 50 ns
Source-Code Compatible With all ’C1x and
’C2x Devices
RAM-Based Operation
– 9K-Words
×
16-Bit Dual-Access On-Chip
Program/Data RAM
– 1056-Word
×
16-Bit Dual-Access On-Chip
Data RAM
2K-Words
×
16-Bit On-Chip Boot ROM
224K-Words
×
16-Bit Maximum
Addressable External Memory Space
(64K-Words Program,
64K-Words Data, 64K-Words I/O, and
32K-Words Global)
32-Bit Arithmetic Logic Unit (ALU)
– 32-Bit Accumulator (ACC)
– 32-Bit Accumulator Buffer (ACCB)
16-Bit Parallel Logic Unit (PLU)
16
×
16-Bit Multiplier, 32-Bit Product
Eleven Context Switch Registers
Two Buffers for Circular Addressing
Full-Duplex Synchronous Serial Port
Time-Division Multiplexed (TDM) Serial Port
Timer With Control and Counter Registers
16 Software-Programmable Wait-State
Generators
Divide-By-1 Clock Option
IEEE Standard 1149.1
(JTAG) Test-Access
Port
Operations are Fully Static
Fabricated Using the Texas Instruments
(TI
) Enhanced Performance Implanted
CMOS (EPIC
)
0.72-
μ
m Technology
Military Operating Temperature Range
–55
°
C to 125
°
C
description
The SMJ320C50KGD digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor
manufactured in 0.72-
μ
m double-level metal CMOS technology.
TI’s military products currently employ three primary processes for the development of known good dies
(KGDs), one of which is applied to the SMJ320C50 device. This process is called the DieMate
system, and
was developed by MicroModule Systems (MMS) and TI’s Materials and Controls Group. This system uses a
membrane probe technique to make electrical contact to the individual die within special carriers. Contact is
made without any disturbances to the bond pads other than typical probe markings. Following burn-in and test,
the dies are simply removed from the carrier, inspected, and packed for shipment.
Future implementation of the SMJ320C50 KGD may employ the hot-chuck-probe process. This process uses
standard probed product that is tested again, this time at full data sheet specifications, in wafer form at speed
and elevated temperature (125
°
C). Each individual die is then sawed, inspected, and packaged for shipment.
A number of enhancements to the basic ’C2x architecture give the ’C50 a minimum 2x performance over the
previous generation. A four-deep instruction pipeline, which incorporates delayed branching, delayed call to a
subroutine, and delayed return from a subroutine, allows the ’C50 to perform instructions in fewer cycles. The
addition of a PLU gives the ’C50 a method of manipulating bits in data memory without using the ACC and the
ALU. The ’C50 has additional shifting and scaling capabilities for proper alignment of multiplicands or for storage
of values to data memory.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1997, Texas Instruments Incorporated
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
EPIC, TI, and DieMate are trademarks of Texas Instruments Incorporated.