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參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 6/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
CONDITIONS
WHEN
SIGNAL IS Z TYPE
NAME
QTY
PRIMARY-BUS INTERFACE
D31 D0
D31- D0
32
I/O/Z
32-bit data port
S
H
R
Data port bus keepers. (See Figure 9)
S
A23- A0
24
O/Z
24-bit address port
S
H
R
R/W
1
O/Z
Read/write. R/W is high when a read is performed and low when a write is performed
over the parallel interface.
S
H
R
STRB
1
O/Z
Strobe. For all external-accesses
S
H
PAGE0 -
PAGE3
1
O/Z
Page strobes. Four decoded page strobes for external access
S
H
R
RDY
1
I
Ready. RDY indicates that the external device is prepared for a transaction
completion.
HOLD
1
I
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23- A0,
D31-D0, STRB, and R/W are placed in the high-impedance state and all
transactions over the primary-bus interface are held until HOLD becomes a logic high
or until the NOHOLD bit of the primary-bus-control register is set.
HOLDA
1
O/Z
Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD.
HOLDA indicates that A23-A0, D31-D0, STRB, and R/W are in the high-impedance
state and that all transactions over the bus are held. HOLDA is high in response to
a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
CONTROL SIGNALS
S
RESET
1
I
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vec-
tor.
EDGEMODE
1
I
Edge mode. Enables interrupt edge mode detection.
INT3- INT0
4
I
External interrupts
IACK
1
O/Z
Internal acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate when a section of code is being executed.
MCBL/MP
1
I
Microcomputer Bootloader/microprocessor mode-select
SHZ
1
I
Shutdown high impedance. When active, SHZ places all pins in the high-impedance
state. SHZ can be used for board-level testing or to ensure that no dual-drive
conditions occur.
CAUTION:
A low on SHZ corrupts the device memory and register
contents. Reset the device with SHZ high to restore it to a known operating condition.
XF1, XF0
2
I/O/Z
External flags. XF1 and XF0 are used as general-purpose I/Os or to support
interlocked processor instruction.
S
R
SERIAL PORT 0 SIGNALS
CLKR0
1
I/O/Z
Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.
S
R
CLKX0
1
I/O/Z
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
S
R
DR0
1
I/O/Z
Data-receive. Serial port 0 receives serial data on DR0.
S
R
DX0
1
I/O/Z
Data-transmit output. Serial port 0 transmits serial data on DX0.
S
R
FSR0
1
I/O/Z
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0.
S
R
FSX0
1
I/O/Z
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0.
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
§
Recommended decoupling. Four 0.1
μ
F for CV
DD
and eight 0.1
μ
F for DV
DD
.
S
R
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