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參數(shù)資料
| 型號： | SMFR-29C516E-31SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16 Bit Flow Through EDAC Error Detection And Correction unit |
| 中文描述： | CMOS SERIES, 16-BIT ERROR DETECT AND CORRECT CKT |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 94K |
| 代理商： | SMFR-29C516E-31SB |
29C516E
7
Rev. D
(09 Dec. 97)
Table 5: 8–Bit Syndrome Word to Bit–In–Error (N22 = ”0”)
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Syndrome Bit
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SY
[
..
]
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hex
3
2
1
0
0
0
0
0
0
N.E.D
MC4
MC5
D
MC6
D
D
D
MC7
D
D
D
D
M
M
D
1
0
0
0
1
MC0
D
D
D
D
D
D
MD7
D
M
D
M
M
D
D
D
2
0
0
1
0
MC1
D
D
M
D
D
D
D
D
M
D
D
M
D
D
MD11
3
0
0
1
1
D
D
MD6
D
D
MD8
D
D
D
M
D
D
D
D
M
D
4
0
1
0
0
MC2
D
D
D
D
M
M
M
D
D
D
MD15
M
D
D
D
5
0
1
0
1
D
M
D
D
D
D
M
M
D
D
MD12
D
D
MD5
D
D
6
0
1
1
0
D
MD9
M
D
D
D
M
M
D
D
M
D
D
M
M
D
7
0
1
1
1
M
D
D
M
M
D
D
D
M
D
D
M
M
D
D
M
8
1
0
0
0
MC3
D
D
M
D
M
D
D
D
D
D
M
M
D
D
M
9
1
0
0
1
D
M
M
D
D
M
D
D
M
M
D
D
D
M
MD13
D
A
1
0
1
0
D
MD10
MD14
D
D
D
D
D
M
D
D
D
D
M
M
D
B
1
0
1
1
D
D
D
M
MD4
D
D
D
M
M
M
M
D
M
D
M
C
1
1
0
0
D
M
D
D
D
D
M
M
D
D
MD3
D
D
MD2
D
D
D
1
1
0
1
MD0
D
D
M
D
D
M
M
D
D
D
M
M
D
D
M
E
1
1
1
0
M
D
D
M
D
D
M
M
D
D
D
M
MD1
D
D
M
F
1
1
1
1
D
M
M
D
D
M
M
M
D
M
M
D
D
M
M
D
Note :
N.E.D
= No Errors Detected
MDx = Memory Data Bit–In–Error
MCx = Memory Check Bit–In–Error
D = Double–Bit–In–Error Detected
M = Multi–Bit–In–Error Detected
7. The 6–Bit Syndrome Word
This feature is available when the N22 pin is driven at a
high level.
7.1. No Errors
If there are no errors in the read Data or Check–Bit, all the
syndrome byte is ”00”. The EDAC flags are inactive.
No Error : SY=00
7.2. Single Bit–Error
A single bit–error in a Memory Data word read (MD[..])
causes three syndrome bits to be set to one. The code
formed indicates which bit of the Memory Data word is
incorrect.
For example, if MD[2] were incorrect, the syndrome byte
would have bits 2, 3 and 4 set to one. The syndrome
decoder of 29C516E EDAC decodes the information in
the syndrome byte and only sets low the error flag CERR.
In correct mode (CORRECT pin active), it inverts (and
hence corrects) the relevant bit in error of the Memory
Data word and provides the expected Data word for the
EDAC controller.
If there is an error in the Memory Check–bit (MC[..]),
only one bit of the syndrome is set to one.
In this case, the syndrome decoder sets low the
correctable error flag CERR, but NCERR does not
change. It does not correct the Check–bit because these
bits are not used by the system.
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