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參數(shù)資料
| 型號： | SM844256KA |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVDS 24-TSSOP |
| 產(chǎn)品培訓模塊： | High Bandwidth Product Overview |
| 標準包裝： | 62 |
| 系列： | RotaryWave™ |
| 類型： | 時鐘/頻率合成器，扇出配送，多路復用器 |
| PLL： | 帶旁路 |
| 輸入： | 晶體 |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 625MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm）裸露焊盤 |
| 供應商設備封裝： | 24-TSSOP 裸露焊盤 |
| 包裝： | 管件 |
| 其它名稱： | 576-3794 |
Micrel, Inc.
SM844256
July 2010
5
M9999-072110-B
LVDS DC Electrical Characteristics
(5, 6, 7)
VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOD
Differential Output Voltage
Figure 1
275
350
475
mV
ΔVOD
VOD Magnitude Change
40
mV
VOS
Offset Voltage
1.15
1.25
1.50
V
ΔVOS
VOS Magnitude Change
50
mV
LVCMOS DC Electrical Characteristics
(6)
VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VIH
Input High Voltage
2
VDD
+0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current (FB_SEL)
VDD = VIN = 3.465V
150
μA
IIH
Input High Current (PLL_BYPASS),
(N_SEL0), (NSEL1)
VDD = VIN = 3.465V
5
μA
IIL
Input Low Current (FB_SEL)
VDD = 3.465V, VIN = 0V
-5
μA
IIL
Input Low Current (PLL_BYPASS),
(N_SEL0), (NSEL1)
VDD = 3.465V, VIN = 0V
-150
μA
AC Electrical Characteristics
(8)
VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
FOUT
Output Frequency
Refer to Frequency Table
75
625
MHz
Tjit()
RMS Phase Jitter (Random)
125MHz, Integration Range:
(1.875MHz – 20MHz)
80
fs
TSKEW
Output-to-Output Skew
Note 9
65
ps
TR/TF
LVDS Output Rise/Fall Time
20% – 80%
100
160
300
ps
ODC
Output Duty Cycle
45
50
55
%
TLOCK
PLL Lock Time
20
ms
Notes:
5. See Figure 4 for load test circuit example.
6. The circuit is designed to meet the DC specifications shown in the above table(s) after thermal equilibrium has been established.
7. Outputs terminated 100 between Q and /Q. All unused outputs must be terminated.
8. The circuit is designed to meet the AC specifications shown in the above table(s) after thermal equilibrium has been established.
9. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points.
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