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參數(shù)資料
| 型號： | SM840004-11KA TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 10/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER LN 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | High Bandwidth Product Overview |
| 標準包裝： | 1,000 |
| 系列： | RotaryWave™ |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng) |
| 輸入： | 晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
2011-2012 Microchip Technology Inc.
Preliminary
DS22280C-page 9
MCP795W1X/MCP795W2X
3.2
Nonvolatile Memory Write
Sequence
Prior to any attempt to write data to the nonvolatile
memory (EEPROM, Unique ID and STATUS register)
in the MCP795WXX, the write enable latch must be set
by issuing the EEWREN instruction (Figure 3-4). This is
done by setting CS low and then clocking out the
proper instruction into the MCP795WXX. After all eight
bits of the instruction are transmitted, CS must be
driven high to set the write enable latch. If the write
operation is initiated immediately after the EEWREN
instruction without CS driven high, data will not be
written to the array since the write enable latch was not
properly set.
After setting the write enable latch, the user may
proceed by driving CS low, issuing either an EEWRITE,
IDWRITE or a SRWRITE instruction, followed by the
remainder of the address, and then the data to be writ-
ten. Up to eight bytes of data can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page.
Additionally, a page address begins with XXXX 0000
and ends with XXXX X111. If the internal address
counter reaches XXXX X111 and clock signals con-
tinue to be applied to the chip, the address counter will
roll back to the first address of the page and overwrite
any data that previously existed in those locations.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 3-2 and Figure 3-3 for more
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the non-
volatile memory write is in progress, the STATUS
register may be read to check the status of the WIP,
WEL, BP1 and BP0 bits. Attempting to read a memory
array location will not be possible during a write cycle.
Polling the WIP bit in the STATUS register is
recommended in order to determine if a write cycle is in
progress. When the nonvolatile memory write cycle is
completed, the write enable latch is reset.
FIGURE 3-2:
BYTE EEWRITE SEQUENCE
FIGURE 3-3:
PAGE EEWRITE SEQUENCE
SO
SI
CS
0
23456789 10 11
1
00
0
01
A6 A5 A4
A1
A3 A2
Address Byte
12 13 14 15 16 17 18 19 20 21 22 23
Instruction
Data Byte
A0
6
7
5
43
2
1
0
High-Impedance
Twc
SCK
A7
SI
CS
910 11
00
0
01
765
432
10
Data Byte 1
SCK
0
2345
67
18
SI
CS
33 34 35
38 39
7
65432
10
Data Byte n (8 max)
SCK
24
26 27 28 29 30 31
25
32
7
6543
210
Data Byte 3
7
6543
210
Data Byte 2
36 37
Instruction
Address Byte
A7 A6 A5 A4 A3
A1 A0
A2
12 13 14 15 16 17 18 19 20 21 22 23
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