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參數(shù)資料
| 型號(hào)： | SM8211M |
| 廠商： | Seiko NPC Corporation |
| 英文描述： | POCSAG Decoder For Pagers |
| 中文描述： | POCSAG碼解碼器尋呼機(jī) |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 145K |
| 代理商： | SM8211M |
SM8211M
NIPPON PRECISION CIRCUITS—1
NIPPON PRECISION CIRCUITS INC.
POCSAG Decoder For Pagers
OVERVIEW
The SM8211M is a POCSAG-standard (Post Office
Code Standardization Advisory Group) signal pro-
cessor LSI, which conforms to CCIR recommenda-
tion 584 concerning standard international wireless
calling codes.
The SM8211M supports call messages in either tone,
numerical or character outputs at signal speeds of
512 bps or 1200 bps using a 76.8 kHz system clock,
or 2400 bps using a double-speed 153.6 kHz system
clock. Note that output timing values for 2400 bps
mode operation are not shown in this datasheet, but
can be obtained by halving the values for 1200 bps
mode operation.
CMOS structure and low-voltage operation realize
low power dissipation, plus an intermittent-duty
receive method (battery-saving function) reduces
battery consumption.
The SM8211M is available in 20-pin SSOPs.
FEATURES
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Conforms to POCSAG standard for pagers
512 or 1200 bps signal speed
Supports tone, numeric or character call messages
Battery-saving function for low battery consump-
tion
BS1 (RF control main output signal) and BS3
(PLL setup signal) 60-step setup time setting—for
BS3, 50.8 ms (max) at 1200 bps and 119.1 ms
(max) at 512 bps
Note that (BS3 setup time)
should be set to
≥
2.
BS2 (RF DC-level adjustment signal) before/dur-
ing reception selectable adjustment timing
6 addresses
×
4 sub-addresses (total of 24
addresses)
1-bit and 2-bit burst error auto-correction function
(messages only)
25 to 75% duty factor signal coverage (during pre-
amble detection)
8 rate error detection condition settings
8 receive mode settings
76.8 or 153.6 kHz system clock (crystal oscillator
or external clock input)
Built-in oscillator capacitor
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(BS1 setup time)
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Built-in input signal filter, with filter ON/OFF and
4 selectable filter characteristics
1.2 to 3.5 V (76.8 kHz system clock) or 2.0 to 3.5
V (153.6 kHz system clock) operating supply volt-
age
Molybdenum-gate CMOS process realizes low
power dissipation
20-pin SSOP
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PINOUT
PACKAGE DIMENSIONS
1
XVDD
2
BS1
3
BS2
4
BS3
5
VDD
6
TEST1
7
TEST2
8
TX-CLK
9
TX-DATA
10
BREAK
11
RST
12
RX-DATA
13
BACKUP
14
SIG-IN
15
VSS
16
ADD-DET
17
RX-CLK
18
SYN-VAL
19
XT
20
XTN
S
5
7.40max
7.20 0.05
0.30 0.15
1
0.65 0.12
0
7
1
2.35
0.68 0.12
4
4
0
+
0.20 0.05
1
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