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參數(shù)資料
| 型號： | SM65MLVD202AD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
| 中文描述： | 多點LVDS線路驅(qū)動器和接收器 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 517K |
| 代理商： | SM65MLVD202AD |
www.ti.com
Output
A/Y
Output
t
pLH
t
pHL
Input
C3
0.5 pF
B/Z
D
0 V
0.9V
V
0 V
t
f
t
r
V
CC
V
CC
/2
0 V
SS
SS
0.1VSS
SS
C1
1 pF
C2
1 pF
V
P(H)
V
P(L)
R1
50
A/Y
B/Z
R1
24.9
t
pZH
t
pHZ
t
pZL
t
pLZ
V
CC
V
CC
/2
0 V
～
0.6 V
0.1 V
0 V
～
-0.6 V
0 V
-0.1 V
DE
Output With
D at V
CC
Output
0 V or V
CC
DE
Output With
D at 0 V
C1
1 pF
R2
24.9
C4
0.5 pF
C2
1 pF
D
C3
2.5 pF
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
SLLS573–DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION (continued)
A.
All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤
1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
B.
C.
D.
A.
All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤
1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
B.
C.
D.
8
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