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參數(shù)資料
| 型號(hào)： | SM5964AIHHKL |
| 廠商： | 新茂國際科技股份有限公司 |
| 英文描述： | 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded |
| 中文描述： | 8位微控制器與64KB的閃存控制器的ISP |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 899K |
| 代理商： | SM5964AIHHKL |
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SyncMOS Technologies International, Inc. SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
AC Characteristic
V
CC
=3.3V
±
10%, V
SS
=0V, t
clk
min = 1/ f
max
(maximum operating frequency)
T
A
=0
to +
℃
70
℃
C
L
=100pF for Port0, ALE and /PSEN; C
L
=80pF for all other outputs unless otherwise specified.
Symbol
FIGURE
PARAMETER
External Clock drive into XTAL1
tCLK
4
Xtal1 Period
tCLKH
4
Xtal1 HIGH time
tCLKL
4
Xtal1 LOW time
tCLKR
4
XTAL1 rise time
tCLKF
4
XTAL1 fall time
tCYC
4
Controller cycle time = tCLK / 12
NOTES :
1.
Operating is 25MHz.
Symbol
FIGURE
PARAMETER
Program Memory
1/tCLK
7
System clock frequency
tLHLL
7
ALE pulse width
tAVLL
7
Address valid to ALE low
tLLAX
7
Address hold after ALE low
tLLIV
7
ALE LOW to valid instruction in
tLLPL
7
ALE LOW to /PSEN LOW
tPLPH
7
/PSEN pulse width
tPLIV
7
/PSEN LOW to valid instruction in
tPXIX
7
Input instruction hold after /PSEN
tPXIZ
7
Input instruction float after /PSEN
tAVIV
7
Address to valid instruction in
tPLAZ
7
/PSEN low to address float
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.3 SM5964A 10/2006
9
MIN
MAX
UNIT
40(1)
20
20
-
-
3.33
-
-
-
10
10
-
ns
ns
ns
ns
ns
ns
MIN
MAX
UNIT
3.0
2tCLK-40
tCLK-40
tCLK-30
tCLK-30
3tCLK-45
0
25
4tCLK-100
3tCLK-105
tCLK -25
5tCLK-105
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Memory
tAVLL
tLLAX
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
8,9
8,9
8
9
8
8
8
8
8
8,9
8,9
9
9
9
8
8,9
Address valid to ALE LOW
Address hold after ALE LOW
/RD pulse width
/WR pulse width
/RD LOW to valid data in
Data hold after /RD
Data float after /RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to /RD or /WR LOW
Address valid to /WR or /RD LOW
Data valid to /WR transition
Data before /WR
Data hold after /WR
/RD LOW to address float
/RD or /WR HIGH to ALE HIGH
tCLK-40
tCLK-35
6tCLK-100
6tCLK-100
0
3tCLK-50
4tCLK-130
tCLK-50
7tCLK-150
tCLK-50
tCLK-40
5tCLK-165
2tCLK-70
8tCLK-150
9tCLK-165
3tCLK+50
0
tCLK+40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UART
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
10
10
10
10
10
Serial port clock time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
12tCLK
10tCLK-133
2tCLK-117
0
10tCLK-133
ns
ns
ns
ns
ns
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| SM5964AL25 | 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded |
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| SM5S11 | Connectors |
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|---|---|
| SM5964AL25 | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded |
| SM5964BW40PP | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:SM5964B 8-Bit Micro-controller 64KB with ISP Flash & 1KB RAM embedded |
| SM5964BW44JP | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:SM5964B 8-Bit Micro-controller 64KB with ISP Flash & 1KB RAM embedded |
| SM5964BW44QP | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:SM5964B 8-Bit Micro-controller 64KB with ISP Flash & 1KB RAM embedded |
| SM5964C25 | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded |
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