參數(shù)資料
型號(hào): SM5907AF
廠商: Seiko NPC Corporation
英文描述: compression and non compression type shock-proof memory controller
中文描述: 壓縮和非壓縮式防震內(nèi)存控制器
文件頁數(shù): 18/30頁
文件大?。?/td> 231K
代理商: SM5907AF
NIPPON PRECISION CIRCUITS-18
SM5906AF
Flag
name
MSRIH
Read
method
READ
90H
bit 1
Meaning
– Indicates that the read sequence has stopped due to internal factors
(not microcontroller commands)
– When the valid data residual becomes 0
– By 90H status read
– When a read address clear (MSRACL) or write address clear (MSWACL) command is recieved
– After external reset
– Indicates residual is not updated because sync data not verified for 1 block
– When sync data is not verified for 1 block (C2PO error etc.)
– When sync data does not occur within a 2352-byte interval
– By 90H status read
– After external reset
– When MSWACL, MSRACL are issued
– Indicates that the valid data residual has become 0
– When the VWA (final valid data's next address)
= RA (address from which the next read would take place)
– Whenever the above does not apply
– Indicates a write to external DRAM overflow state
– When the write address (WA) exceeds the read address (RA).
(Note: This flag is not set when WA=RA through an address initialize or reset operation.)
– When the read address (RA) is advanced by the read sequence
– When a read address clear (MSRACL) or write address clear (MSWACL) command is issued
– After external reset
– Indicates that the write sequence (input data entry, DRAM write) is operating
– By the 80H command when MSWREN=1
– When conforming data is detected during compare-connect operation
– When the connect has been performed after receiving a direct connect command
– When the FLAG6 flag=1 (above)
– When the OVFL flag=1 (above)
– When the BOVF flag=1 (above)
– By the 80H command when MSWREN=0
– By the 80H command when MSDCN1=1 or MSDCN2=1 (compare-connect start command)
– By the 80H command when MSON=0
– After external reset
Note. Reset conditions have priority over set conditions. However, simultaneous MSWREN = 1
and compare-connect operation has precedence over WRSQ.
– Indicates that the read sequence (read from DRAM, data output) is operating
– By a new 80H command when MSRDEN=1 and the MSEMP flag=0 (above)
– Whenever the above does not apply
Set
Reset
SYNCWAR
READ
90H
bit 0
Meaning
Set
Reset
MSEMP
READ
91H
bit 7
Meaning
Set
Reset
Meaning
Set
OVFL
READ
91H
bit 6
Reset
WRSQ
READ
91H
bit 5
Meaning
Set
Reset
RDSQ
READ
91H
bit 4
Meaning
Set
Reset
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