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參數(shù)資料
| 型號： | SM5170 |
| 廠商： | Seiko NPC Corporation |
| 英文描述： | PLL Synthesizer IC |
| 中文描述： | PLL合成器集成電路 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 119K |
| 代理商： | SM5170 |
SM5170AV
NIPPON PRECISION CIRCUITS—4
Electrical Characteristics
V
SS
= 0 V, V
DD1
= 0.95 to 1.2 V, V
DD2
= 2.0 to 3.3 V, T
a
=
10 to 60
°
C
DATA, CLK, and LE timing
Parameter
Symbol
Condition
Rating
Unit
min
typ
max
VDD1 operating current consumption
I
DD1
I
DD2
I
st1
I
st2
Note 1.
1. V
DD1
quency, OPR = HIGH, no output load, typ condition : V
2. V
DD1
DD2
quency, OPR = HIGH, no output load, typ condition : V
3. V
DD1
DD2
4. V
DD1
DD2
5. DB output is derived from the V
6. DB output is derived from the V
7. DO output is derived from the V
8. DO output is derived from the V
= 1.0 to 1.05V, V
DD2
= 2.7 to 3.3 V, f
FIN
= 310 MHz (300 mVp-p sine wave), f
= 1.0 V
= 310 MHz (300 mVp-p sine wave), f
= 3.0 V
XIN
= 14.4 MHz (300 mVp-p sine wave), 25 kHz comparator fre-
DD1
–
1.1
1.9
mA
VDD2 operating current consumption
Note 2.
= 0.95 to 1.2 V, V
= 2.7 to 3.3 V, f
FIN
XIN
= 14.4 MHz (300 mVp-p sine wave), 25 kHz comparator fre-
DD2
–
0.003
–
VDD1 standby current
Note 3.
= 1.0 V, V
= 0 V, V
= 3.0 V, OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V)
= 2.7 to 3.3 V, OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V), typ condition : V
supply. DB-pin condition select bit = (00001)
supply. DB-pin condition select bit = (11111)
supply. V
DD2
DD2
DD2
–
0.7
–
μA
VDD2 standby current
Note 4.
DD2
= 3.0 V
–
0.01
10.0
FIN maximum operating input frequency
f
max1
300 mVp-p sine
wave
V
DD1
= 0.95 to 1.2 V
300
–
–
MHz
V
DD1
= 1.0 to 1.2 V
330
–
–
XIN maximum operating input frequency
f
max2
f
min1
f
min2
V
FIN1
300 mVp-p sine wave (external input)
25
–
–
MHz
FIN minimum operating input frequency
300 mVp-p sine wave
–
–
40
MHz
XIN minimum operating input frequency
300 mVp-p sine wave (external input)
–
–
9
MHz
FIN input amplitude
f
FIN
f
FIN
AC coupling
= 300 MHz, AC coupling
0.3
–
–
Vp-p
V
FIN2
= 330 MHz, V
DD1
= 1.0 to 1.2 V,
0.3
–
–
XIN input amplitude
V
XIN
f
XIN
= 25 MHz, AC coupling (external input)
0.3
–
–
Vp-p
OPR, CLK, DATA, LE LOW-level input
voltage
V
IL
–
–
0.3
V
OPR, CLK, DATA, LE HIGH-level input
voltage
V
IH
V
DD2
0.3
–
–
V
FIN LOW-level input current
I
IL1
I
IL2
I
IH1
I
IH2
V
DOL
V
IL
= 0 V
–
–
60
μA
XIN LOW-level input current
–
–
10
μA
FIN HIGH-level input current
V
IH
= V
DD1
–
–
60
μA
XIN HIGH-level input current
–
–
10
μA
DB LOW-level output voltage
Note 5.
DD2
DD2
DD2
2
2
, V
, V
DD2
DD2
= 2.7 to 3.3 V, no load
= 2.7 to 3.3 V, no load
0.5
V
DB HIGH-level output voltage
V
DOH
Note 6.
V
DD2
0.5
V
DO LOW-level output current
I
DOL
I
DOH
I
OZL
I
OZH
t
SU1
t
SU2
t
H
Note 7.
= 2.7 to 3.3 V, V
= 2.7 to 3.3 V, V
OL
OH
= 0.4 V
= V
1.0
–
–
mA
DO HIGH-level output current
Note 8.
supply. V
DD2
0.4 V
1.0
–
–
mA
DO, DB tristate output high-impedance
leakage current
V
OL
= 0 V
–
–
100
nA
V
OH
= V
DD2
–
–
100
nA
DATA
→
→
CLK setup time
See the timing diagrams.
2
–
–
μs
CLK
LE setup time
2
–
–
μs
Hold time
2
–
–
μs
V
IH
t
SU1
t
SU2
V
IH
V
IH
V
IH
t
H
DATA
CLK
LE
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