參數(shù)資料
型號： SM320C6416DGADW60
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, CPGA570
封裝： 33 X 33 MM, CERAMIC, FCPGA-570
文件頁數(shù)： 81/134頁
文件大?。?/td> 1997K
代理商： SM320C6416DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
50
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
DESCRIPTION
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
EMIFB (16-bit) DATA||k
BED15
F8
BED14
J10
BED13
D7
BED12
C5
BED11
H10
BED10
G9
BED9
C6
BED8
E8
I/O/Z
IPU
EMIFB external data
BED7
E9
I/O/Z
IPU
EMIFB external data
BED6
F9
BED5
G10
BED4
J11
BED3
D9
BED2
D8
BED1
H11
BED0
F10
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)
MCBSP2_EN
AB4
I
IPD
McBSP2 enable pin. This pin works in conjunction with the PCI_EN pin to enable/disable other
peripherals (for more details, see the Device Configurations section of this data sheet).
CLKS2/GP8§
W7
I/O/Z
IPD
McBSP2 external clock source (CLKS2) [input only] [default] or this pin can also be
programmed as a GPIO 8 pin (I/O/Z).
CLKR2
W4
I/O/Z
IPD
McBSP2 receive clock. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0),
this pin is tied-off.
CLKX2/
XSP_CLK§
W5
I/O/Z
IPD
McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O).
DR2/XSP_DI§
Y4
I
IPU
McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is
connected to the output data pin of the serial PROM.
DX2/XSP_DO§
R9
O/Z
IPU
McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin
is connected to the input data pin of the serial PROM.
FSR2
V6
I/O/Z
IPD
McBSP2 receive frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin
= 0), this pin is tied-off.
FSX2
U7
I/O/Z
IPD
McBSP2 transmit frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin
= 0), this pin is tied-off.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§ For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins except CLKS2/GP8 are standalone
peripheral functions for this device.
|| These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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