參數資料
型號: SLE 66cx320p
廠商: SIEMENS AG
英文描述: 16-Bit Security Controller with Memory Management Unit in 0.25 CMOS Technology 64 Kbyte ROM, 3 Kbytes RAM, 32 Kbyte EEPROM 1100-Bit Advanced Crypto Engine and 64-Bit DES accelerator(16位安全控制器(帶64-KB ROM,3K RAM, 32KB EEPROM))
中文描述: 16位安全控制器的存儲器管理單元在0.25 CMOS工藝64字節(jié)ROM,3字節(jié)的RAM,32KB的EEPROM的1100位高級加密引擎和64位DES加速器(16位安全控制器(帶64 KB的光盤,3K內存,32KB的EEPROM的))
文件頁數: 6/7頁
文件大?。?/td> 56K
代理商: SLE 66CX320P
SLE 66CX320P
Preliminary Short Product Information
6 / 7
07.99
General Description
SLE 66CX320P is the first product of Infineon Technologies high end security controller family in
advanced 0.25 μm CMOS technology. The CPU provides the high efficiency of the SAB 8051
instruction set extended by additional powerful instructions together with enhanced performance,
memory sizes and security features. The internal clock frequency can be adjusted up to 15 MHz
independent of the clock rate of the terminal with the help of the PLL.
The controller IC offers 63 Kbyte of User-ROM, 256 bytes internal RAM, 2048 bytes XRAM and 32
Kbytes EEPROM. The Memory Management Unit allows a secure separation of the operating
system and the applications. Furthermore the MMU makes a secure downloading of applications
possible after the personalization of a card. These new features suit the requirements of the next
generation of multi application operating systems. For code compatibility to the SLE 66CxxS
family, a transparent mode for the MMU is established which allows to keep the memory mapping
of the SLE 66CxxS products.
ROM
64 KByte
Sleep Mode
Logic &
Sensors/Filters:
Voltage
Clock
Reset
PLL
EEPROM
32 KByte
16-bit
Timer
DES
Accelerator
Voltage
Regulator
A ddre s s /D a ta
B us
16-bit CPU
with MMU
& ECO 2000
Instruction Set
Random
Number
Generator
XRAM
2 KByte
Advanced
Crypto Engine
CRC
UART
Figure 2
Block Diagram SLE 66CX320P
The CRC module allows the easy generation of checksums according to ISO 3309 (16-Bit-CRC).
To minimize the overall power consumption, the chip card controller IC offers a sleep mode. The
UART supports the half-duplex transmission protocols T=0 and T=1 according to ISO 7816-3. All
relevant transmission parameters can be adjusted by software, as e.g. the clock division factor,
direct/inverse convention and the number of stop bits. Additionally, the I/O port can be driven by
communication routines realized in software.
The Advanced Crypto Engine is equipped with its own RAM of 700 bytes and supports all of today
known public-key algorithms based on large integer modular arithmetic. It allows fast and efficient
calculation of e.g. RSA operations with key lengths up to 2048 bit.
The DES accelerator consists of two modules. The DES module supports symmetrical crypto
algorithms according to the Data Encryption Standard in the Electronic Code Book Mode. The EC2
module accelerates the multiplication in GF(2
n
) and therefore the operations for elliptic curve
cryptography.
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