參數(shù)資料
型號: SLA 24C08
廠商: SIEMENS AG
元件分類: DRAM
英文描述: 8Kbit (1024 × 8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(8K位 (1024 × 8 位) CMOS串行EEPROM(帶IIC控制))
中文描述: 8Kbit(1024 × 8位)串行的CMOS EEPROM,帶有國際進口同步2線巴士(8K的位(1024 × 8位)的CMOS串行EEPROM的(帶控制國際進口許可證))
文件頁數(shù): 9/23頁
文件大小: 323K
代理商: SLA 24C08
SLx 24C08/16
Semiconductor Group
9
1999-02-02
The conventions for the serial clock line and the bidirectional data line are shown in
figure 4
.
Figure 4
I
2
C-Bus Timing Conventions
for START Condition, STOP Condition, Data Valida-
tion and Transfer of Acknowledge ACK
Standby
Mode in which the bus is not busy (no serial transmission, no
programming): both clock (SCL) and data line (SDA) are in high
state. The device enters the standby mode after a STOP condition
or after a programming cycle.
High to low transition of SDA when SCL is high, preceding all
commands.
Low to high transition of SDA when SCL is high, terminating all
communications. A STOP condition initiates an EEPROM
programming cycle. A STOP condition after reading a data byte
from the EEPROM initiates the Standby mode.
A successful reception of eight data bits is indicated by the
receiver by pulling down the SDA line during the following clock
cycle of SCL (ACK). The transmitter on the other hand has to
release the SDA line after the transmission of eight data bits.
The EEPROM as the receiving device responds with an
acknowledge, when addressed. The master, on the other side,
acknowledges each data byte transmitted by the EEPROM and
can at any time end a read operation by releasing the SDA line (no
ACK) followed by a STOP condition.
Data must change only during low SCL state, data remains valid
on the SDA bus during high SCL state. Nine clock pulses are
required to transfer one data byte, the most significant bit (MSB)
is transmitted first.
START Condition
STOP Condition
Acknowledge
Data Transfer
1
2
8
9
1
9
ACK
ACK
START Condition
Data allowed
to Change
STOP Condition
Acknowledge
SCL
SDA
IED02128
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