參數(shù)資料
型號: SL38000ZI-15AHT
廠商: Silicon Laboratories Inc
文件頁數(shù): 4/10頁
文件大?。?/td> 0K
描述: IC CLK 4PLL VCXO SSCG 28TSSOP
標(biāo)準(zhǔn)包裝: 2,000
系列: EProClock®
類型: *
PLL: 帶旁路
輸入: 時鐘,晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:11
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
Rev 2.3, July 9, 2010
Page 3 of 10
SL38000-15AH
Pin Description
Pin
Number
Pin Name
Pin
Type
Pin Description
1
XIN/CLKIN
Input
External crystal oscillator input. XIN=25.000MHz. If crystal with CL=18pF is
used no external crystal load capacitors are needed. See Note-2 below.
2
OE
Input
Output enable for CLK1 (12.000MHz) pin. OE=1 CLK1 is enabled. OE=0 CLK1
is disabled. Refer to Table 2. Weakly pulled-up to VDD (20
0kΩ-typ).
3
CLK2
Output
125.000MHz clock output. No Spread.
4,12,13,
15,18,25
N/C
N/A
No connect (leave these pins floating).
5
VDDO1
Power
Power pin for SSCLK1=133.333MHz. 3.3V+/-10%. Power supply ramp on this
pin should be the same as VDD power ramp on pins 6, 26 and 27. See Note-1
below.
6,26,27
VDD
Power
3.3V+/-10%.
7,8,9,10,
20,21
VSS
Power
Power supply ground for VDD and VDDO pins.
11
REFOUT
Output
25.000MHz. (Same as crystal input frequency)
14
SSCLK1
Output
133.333MHz clock output with spread option. Spread is off if SSON=0. Spread
is on if SSON=1. Refer to Table 1.
16
SSCLK2
Output
50.000MHz clock output with spread option. Spread is off if SSON=0. Spread
is on if SSON=1. Refer to Table 1.
17
SSON
Input
Spread control pin for SSCLK1 (133.333MHz) and SSCLK2 (50.000MHz)
clocks. If SSON=1 spread is on. If SSON=0 spread is 0% (no spread). Refer to
Table 1 for spread % values. Weakly pulled-
down to VSS (200kΩ-typ).
SSON is powered by VDDO3 and SSON=1=VDDO3=2.5V.
19
CLK1
Output
12.000MHz clock output. No Spread.
22
VDDO3
Power
Power pin for CLK1=12.000MHz. 3.3V+/-10%. Power supply ramp on this pin
should be the same as VDD power ramp on pins 6, 26 and 27. See Note-1
below.
23
VDDO2
Power
Power pin for SSCLK2=50.000MHz. 3.3V+/-10%. Power supply ramp on this
pin should be the same as VDD power ramp on pins 6, 26 and 27. See Note-1
below.
24
PD#
Input
Power down control pin. PD#=1 is normal operation. Device is turned off if
PD#=0. Refer to Table 3. Weakly pulled-
up to VDD (200kΩ-typ).
28
XOUT
Output
External crystal output. If crystal with CL=18pF is used no external crystal load
capacitors are needed. See Note-2 below.
Note-1: VDDO
≤VDD at all times or all VDD and VDDO pins must be connected to same common VDD
power supply.
Note-2: Xin and Xout pin capacitances are programmed as 34pF. Including 2pF parasitic PCB
capacitances at each pin, the total capacitance value becomes 36pF. If a crystal with 18pF is used, no
external capacitance is required since these capacitance values matches the crystal CL=18pF
requirement for nominal +/-0ppm crystal accuracy.
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